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Posts posted by KWaris

  1. I personally see no better education at fundamental level that A Level Computing from AQA board. This is a UK board qualification and you could take exam in January or May. Exam is the best part, scoring an A might get you in Howard university.

    I wont mind taking A Level ICT and Applied ICT as well.

  2. Hello Everyone,

    I have been pondering over the problems of noise I had always seen on analogue signals but never got rid of it. Today I was just learning about scan engine and I found that If I add my analogue module under cRIO target for the scan mode, and deploy the variables and see the analogue values on the distrubed manager, these continuously changing analogues on the second decimal are not really random but if we see the graphical trends in the distributed manager, these continously changing analogue values for any channel actually make a perfect sine wave vertically shifted by -3.1V.

    These readings I have found using NI 9205 module with no transducers/sensors connected on the modules terminals. I just have the cRIO on my desk with all the modules inserted into the slots. I am sure that the transducer signal is always superimposed with this sine wave signal. What is the reason for this sine wave signal when nothing is connected. Can I get rid of it ?

    Thanks for reading

    Kind Regards

  3. yes it is the third decimal and I am not doing averaging.

    This is strange that the differential wiring configuration for this module looks very similar to single ended configuration.

    According to instructions, all -ve ends and the common pins must be grounded to a stable ground. In my case, the electrical enclosure has got three grounds. ( Mains supply 230 V for the pc, 24V for Compact RIO and analogue ground for analogues). Compact RIO is fed from a linear regulated power supply. The analogue ground commons up all the negatives of the analogue signal and common terminals on 9205 card. I dont think the analogue ground and compactRIO ground are different.

    But really, I cant produce another ground. 230V supply is single phase power cable with the external ground. So there are three cores coming inside this electrical

  4. I started doing projects to acquire analog signals now about a year ago. First time, I read the signals using NI 9205, I wondered why the readings were not stable. ( I was expecting study signal I observe using Digital Multimeter).We minimized the losses completely by grounding properly, using both single ended and differential configuration. This issue however still is outstanding.

    I think I might have not used some proper programming to acquire the analog data. I might be oversampling the signals etc. So I thought lets put the question in writing.

    The while loop in FPGA of the compact rio includes wait functions wired to 100us. Minimum time between conversion = 6.25us.

    Rest assured the signals are correct, 10 points calibration returned the correct results. These errors are withing the Full scale deflection maximum error specification. These however look very bad on the front panel. I am not in the position to say that we can design very precise analog based control systems. We have been questioned in the past about our wiring techniques, grounding methods after our customers observed these erratic readings.

    I wonder how everybody else is doing this? Thanks for your time

    Kind Regards


  5. Hello

    I am struggling to fix the number of decimal places for the digital displays of Labview Gauges. I did all the settings in the properties e.g number of decimal points, minimum and maximum values etc. However, I still see the analgue values (from 9205 module) going from 3 decimal places to 4 decimal places. Its typical with the gauges only. If I use a numeric control instead, this doesn't happen. However, for me its now too late to hide the digital displays and start adding seperate numeric controls. Most of the gauges are the cluster of few analog channels. And adding different numeric indicator gauges at this stage could be really bit dangerous as I might not meet the project deadline.

    Is it possible to fix the number of decimals of these gauges. I am sure I am missing here something very simple.

    Thanks for the help

    Kind Regards


  6. I have now managed to close my application (all loops). As I had used the shift registers for error wires in all the loops, I just used the clear error vi outside all the cases just before the shift register to the right side of each loop. I could have perhaps created an error handler vi to handle the errors here and then merge the error wires outside the while loops and used simple error handle vi to find what error occured in the application. I have however realized that merging all the error wires and using simple error handle vi will only report the first error and ignore all the others. I searched for SEH (structured error handler library)for labview 2011 but been very unsuccessful.

    Is this library available free? Or are there some other third party libraries which could be used to handle the errors (e.g retry, ignore, report etc)

    Thanks for the help

  7. Hello Rolfk

    Believe me this is real software engineering :yes: .

    When I want to quit, I click stop button this resides in Producer loop. This triggers an event and a command is sent to the consumer loop to shutdown the application. Shutdown case in the consumer loop contains the queue references to all the loops and send the command to execute the shutdown cases. In the shutdown case, the while loop loop termination input is wired to true to stop all the loops.

    7 of them stops, three of them containing these UDP loops dont stop. I will follow your tips and hopefully it all works. :thumbup1:

  8. Hello Rolfk,

    These are the timeout and peer disconnecting messages. Error 56 and Error 66.

    It is suitable for this application to be restarted so attempting to reconnect is very convenient. This is 10 loops architecture, all other starts fine and all the codes in other loops work. It is only these 3 loops where I am calling the devices over UDP which sometimes donot initialize properly. As I said the Error 56 and Error 66 occur when this happens. There is no set rule here sometimes it is Error 56 and sometimes it is Error 66. But if I keep closing the application and re-opening it then eventually the connection is established successfully. I could think the only best way here is perhaps to completely close down the application and restart it again and I can only do it by doing CTRL+ALT+DEL. There is something stopping these three loops to shut down. I used Clear errors thinking if there is an error which is stopping the loop to shutdown, it will be then ignored. It is still not working.

    Any suggestions?

    Kind Regards


  9. A very odd this happened to my project!

    One concept I still get to grasp fully is error handling! This project is a multiloop project. All the vis have auto-error handling enabled.

    When I started doing this few weeks ago, I always had thought why if there was an error, labview is showing that dialog box with message number and an option to continue or stop.

    Then now all of sudden when I plugged in my computer, the application started throwing those messages. So I am here not aware what changed between yesterday and today. Any ideas!

  10. I wonder if I could be very clever and find the way out of my problem here.

    I am communicating with a device over UDP and for some reason, the device doesn't often establish communication with my Labview Executable on the first attempt.

    I run it, it fails, I then use CTRL+ALT+Delete to shut it down. I donubleclick the executable ICON on the desktop again and I sometimes do it five or six times then finally the communication is established and it all works.

    I wonder if I could add some code in the application to automate this process. One of the way I could now think to do is by creating another vi and call my current vi dynamically and add all those conditions into cluster, call this cluster (by wiring to the output terminal of the current main vi into new main vi) and monitor my cluster in the new main vi to see if the conditions are true if so continue or reload the current vi until those conditions are met? Is it the right way to do this? Or can I make my life easier and applcation more stable by doing something different?

    Kind Regards


  11. I most often use it when I have an array of booleans or cluster of booleans( in which case I also use cluster to array function) and these are on the front panel and I want to trigger different events or conditions when each one of them is clicked. I use search 1d array function to determine if the boolean control is clicked. If index returned it not -1 I use case structure to define what I want to do.

    I just tried to give an example of where this function could be used. Its a powerful function and could be used in many ways. Just use your imagination

  12. why not just drop the stacked sequence structure on the block diagram. Drop one of the flat sequence structure inside stacked sequence. Right click the frame of the stacked sequence and add the frame. Inside the new frame, add the second flat sequence. And keep doing it until all flat sequence frames are placed.

    This is just to do what you want to do. I would perhaps take the advices above, convert the code into vis and the state machine. Using proper labview architecture, the application could be extended and scaled in future

  13. .hooovaah, I wonder how you getting 42 nseconds by multiplying loop rate in ms seconds with 1000?

    The thing is, one thing is obvious. We should rather not put anytime in a loop. The loop will run as fast as it could to execute. This is never going to stall the application. And perhaps best approach is to do what you did, find the minimum rate and then just add some more time for the update of the user interface?

    Unfortunately, especially in windows where most of us may rely on the timeout inputs of the enqueue function to execute some code periodically, we are really limited to 1ms to timeout the queue. Otherwise, that piece of code which we include will not run.

    Perhaps in the later versions, we could use a smaller number.

    I apologize Hoovaah, you did the right thing. I am just doing the things a bit fast today without thinking.

  14. I have a very large application not written very carefully but I could see all subvis are linked using error clusters. There are 12 loops on the block diagram and all of them are merged together in the end and all queues are released properly. This vi calls FPGA, and TTL power supply and also communicates with few other third party instruments.

    At the moment I have no FPGA connected, I run the vi and obviously it wont go anywhere as the CompactRIO is not wired to the PC. The application however doesn't stall either. It is hard for me to find all the faults ( if there are any) in the application. I am only interested in running it, design few state machines, make sure they all work and be able to close the application by pressing the stop button.

    Now because of the fact the hardware is not connected to my pc, I would like the application to at least return the errors. I added the Simple error handler vi where all the queues are released and clicked the stop button but this does not return any error. I added few booleans to see which loop stops and which doesn't. I noticed that only the producer and consumer loops were stopped. Rest of them did not even go to the Stop case.

    In order to finish my work I could just cover all the cases where the instruments are called in the diagram disable structure and finish the state machines. But I may consequently miss some errors which are not there due to the hardware but for someother reason.

    I am just downloading Structured error handler library and I hope that by putting the express vi in each case of each loop and setting it to notify, it will keep telling me where the errors are. And then I can see if this is the pure hardware problem and just set the diagram disable structure to disable for that part of the case structure, run the main vi again and find the next error? Can I achieve this?

    My biggest worry is certain UDP vis in one of the loop in the project. These are certain pre-built vis I received from my colleague before he left us. I remember he telling me once that these vis when incorporated in a project sometime initialize/shutdown with no problem, but sometimes when you start the application and you send the query to the instrument, it wont work. The other times it will work fine. During shutdown, sometimes they shutdown smoothly, but sometimes they stop the application and the only way to get out of it is by using CTRL+ALT+Delete.

    This really makes the whole application unreliable to the end-user. I just did some research and found this UDP error are due to the communication timeout problem and could be eliminated by using Structured Error Handler VI. We could just set it to retry (infinite) and it will make sure that the application starts fine.

    I believe the application must stop in all conditions when the 'Stop' button is clicked. Is this achievable?

    it might be a valid reason to give to the end-user that 'this occurs due to the timeout problem, Please click the stop button and then double click the icon on the desktop'

    Sorry about the big essay. Hope I am on the right track? Thanks for reading.


  15. This issue for me is still outstanding. I have both 2010 and 2011 versions of labview. Building executable in labview 2010 and running on a pc with no labview development suite works.

    Doing the same but with application built in Labview 2011 doesn't help. I forced the front panels and tried all sorts e.g including the libraries in source files. I even copied all the dll files in system 32 to the pc and it still didn't work.

    Following some thread on NI, I found somebody had the similar problem but they fixed it by repairing Advanced Signal Processing Toolkit and installing Advanced Signal Processing Run Time Engine In Deployment (without Labview suite) PC and it worked.

    But that even didn't work. I ended up installing whole Labview 2011 development suite and that is working. Unfortunately, I cant deliver the pc with full development suite and I have no idea what I could do to fix it.

    Perhaps reinstalling 2011 from scratch in the development computer?


  16. I created a cluster containg 10 indicators of different types. I then created the array of this cluster.

    Each row of the array represents the data of each cycle. Here is the problem.

    Say the first control in the first row of the array is start time. When I programatically add (lets say time) to this cell using insert into array function, All the cells in 'start time' column fill with this number.

    I think there might be some option to stop the array from doing this which I am not familiar with. Any comments?

    Please find attached this control

    6286_Operation Result Array.ctl

  17. I personally believe that such High Speed application should be done in RT and FPGA. I recently did all data acquisition(using DMA FIFO) in FPGA, then streaming data from RT to windows using network stream. It was all good. Then I was told to add some machine logic in FPGA, I did it but the built exceeded 100% resource utilization. I decided to perform this logic in RT.

    So I ended up adding 5 timed loops all set to different priorities in RT and then I used Network-published shared variable to stream this data form RT to windows. But to no avail!

    I found that there was a delay of at least 35 seconds before I started seeing some values on the operation screen( a simple HMI to display the status of the machine). And I was having further deployment issues.

    I dont know what the right way to use RT target especially in CompactRIO.

    I used the following method but it didn't quite work!

    Data acquisition Data- Transducers to AI card to FPGA to DMA FIFO (target to host) to DMA FIFO (read) to network stream (write) and then reading it back on windows.

    Control Logic- Limit switched to FPGA to RT to Networked Publish Shared Variables to HMI- but that really didn't work. (Sometimes, Variables wont update or show any change).

    Will appreciate comments

    Kind Regards


  18. Is it possible to achieve the speed faster than 1ms for a vi running under windows target. All the data communication functions such as queues doesn't seem to be timed out in less than 1ms and I tried to monitor the loop rate using tick count function but these also monitor in ms scale and do not return value in DB format.

    I will be amazed if it is not possible to run a windows vi as fast as 1us when the processor could run in GHZ.

    Will appreciate comments on this. I am working on a high speed control application and it is not suitable to use the RT target for this application.

    Kind Regards


  19. Hello there,

    I am developing an application in which functions from advanced signal processing toolkits are used.

    If I run the application on development computer. It works fine.

    When I create build and deploy the executable on deployment computer with no labview development suite, I get the following error

    LabVIEW resource not found.

    An error occurred loading VI "NI_AALBase.lvlib:Median.vi".

    LabVIEW load error code 3: Could not load front panel

    I included the above .lvlib as a support file by including it in always included box but I still get the same error. Is it possible to fix this problem?



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