Search the Community
Showing results for tags 'boolean input'.
Found 1 result
CAR# 378165 LabVIEW Version 11.0.1f2 In a VI for a FPGA target, if an error cluster is wired to one input of an OR gate that has a Boolean wired to the other input, then in the "generate intermediate files" process that precedes the Xilinx bitfile generation, "stage 1 of 7" (analyzing VI hierarchy) will very repeatably crash while processing the VI. See attached PDF.