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Found 1 result

  1. I am having trouble realising an FIR filter in Spartan 3E XUP board. I have succesfully compiled the FPGA VI generated from "Generate IP" (However, IP Builder sub menu is not existing this board in Project explorer as given in FPGA IP bulider tutorial). The FPGA Vi wil be running in SCTL receiving FXP data elements. But an array of data is required for the filtering to happen. How to do this without DMA FIFO as the board supports only Target scoped FIFO?
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