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Found 6 results

  1. Hi We have an application where we need to have a custom PCIe board transfer data to the PC using DMA. We are able to get this to work using NI-VISA Driver Wizard for PXI/PCI board. The recommended approach is to have VISA allocate memory on the host (PC) and have the PCIe board write to it (as seen below). While this approach works well, the memory allocated by VISA for this task is quite limited (~ around 1-2MB) and we would like to expand this to tens of MB. Note: The documentation (and help available on the web) regarding these advanced VISA function (for inst
  2. I have a system that composed of 1- NI-cRIO9014 2- Chassis (cRIO-9104) 3- Three Mods. NI9215 I use this system to capture 12 analog signals. What is the relation between sampling frequency defined by time delay in fpga.vi and the Requested number of Elements defined in FIFO?. When I use a time delay of 40us and Requested number of Elements 8191, it produces wrong data. When I use a time delay of 40us and Requested number of Elements 65535, it produces correct data.
  3. Hello! Is there anything similar to "DMA MEMORY" that behaves like DMA FIFO, but without the FIFO part? I would like to transfer 1000 bytes of data from the FPGA to the cRIO host and 1000 bytes of data from the host to the FPGA and I don't care about old data - I only need the latest data. Ideally I would like to have two pieces of memory, each 1000 bytes long. One piece that can be written from the FPGA and read from the host and the other piece that can be written by the host and read by the FPGA, so that the first byte of data is always on the address 0. DMA FIFO is not a viable
  4. I am having trouble realising an FIR filter in Spartan 3E XUP board. I have succesfully compiled the FPGA VI generated from "Generate IP" (However, IP Builder sub menu is not existing this board in Project explorer as given in FPGA IP bulider tutorial). The FPGA Vi wil be running in SCTL receiving FXP data elements. But an array of data is required for the filtering to happen. How to do this without DMA FIFO as the board supports only Target scoped FIFO?
  5. Dear All, I have a question regarding to FPGA FIFO, specifically DMA from Host to Target (FPGA). As an Example, I have a 1D array containing 10x2000 elements stored inside the host side Buffer. At the FPGA side, I want to use 'host to target-read' to read fixed amount of elements from the host side buffer, for example exact 2000 elements. Moreover I want to hold onto the data (2000 elements) for a certain amount of time (example 10s) before reading again 2000 elements from the buffer. Does anyone have a clue how to do this? Thank you so much! Yang
  6. Hi everyone, I will be presenting TS1360: "Implementing an Efficient Moving Average Filter in LabVIEW FPGA" on Thursday 1-2pm. Room 16B. These techniques are relevant for developing any sort of code on the FPGA, not necessarily filters. Many of the findings are a bit counter-intuitive for someone used to developing regular LabVIEW code or even Real-Time LabVIEW code. Hope to see some of you there or bump into you in the corridors of the Convention Centre! Cheers, Neville.
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