LV RIO ... where exactly is the bitstream stored?

[flintstone]

Hi,

me again .

I am currently in big confusion about the way LV stores the FPGA configuration bitstream for a RIO device. As mentioned in other posts I have a setup where my project is transfered to a PXI controller where some SW framework loads it in a plugin approach. My project employs a R series FPGA board. I had some confusing experiences with this where the oscilloscope showed clearly different behavior than what the implementation should do. After some time I noticed it was seemingly and old bitstream used. I then introduced a revision number for my FPGA design that is set to a constant in the FPGA top-level VI and actually I saw that there was the wrong bitstream being loaded.

The way I do it is with the "Open FPGA VI Reference" VI that is configured to use a bitstream. The bitstream is actually copied to the build destination directory and is the latest according to the timestamp. But I doubt that really this bitstream is used because a) I once deleted it on the target system and my design would still boot happily boot without throwing an error when calling the Open FPGA VI Reference VI and b) my VI that calls the Open FPGA VI Reference VI is about 1 MByte big. Somehow I have the feeling that the FPGA VI is compiled into this VI although this is not stated anywhere.

So the question is what might I be doing wrong here or whether this is the way it is supposed to work. At the moment every time I did a new synthesis of the FPGA is explicitly open the "Open FPGA VI Reference" VI configuration dialog and point it to exactly the same bitfile and with this I have not seen a "wrong bitstream" problem but it is not nice to do so.

Best regards

flintstone

[Zyl]

Hi !

I think now (LV2011 for sure) you can explicitly set the "Open FPGA Reference" VI to load a bitfile according to a build specification. Doing this may prevent loading an old bitfile...

[JamesMc86]

How are you transferring the code to the PXI?

I think you are correct that the bitfile will be included with the VI (though I have to say I have not done this as a source distribution rather than an rtexe before. this means you may need to reopen the VI to link to the new bitfile rather than transferring the file separate with the VI. This is certainly the case wi rtexe but I may need to double check this with the source method.

The other option is you can burn the bitfile directly to the FPGA rather than depending on the Rt vi to download it.

Definitely in the VI:

Note  The Open FPGA VI Reference function extracts the bitstream from the compiled FPGA VI or bitfile and stores the bitstream when you save the host VI. The bitstream contains the programming instructions LabVIEW downloads to the FPGA target.

from http://zone.ni.com/reference/en-XX/help/371599C-01/lvfpgahost/open_fpga_vi_reference/

[flintstone]

Oh, I have to apologise I did not find this although it is the first thing I should have checked ... shame on me.

But it brings up a second question: "When the Open FPGA VI Reference function first executes on the block diagram, it checks whether the compiled FPGA VI already exists on the FPGA target. If the compiled FPGA VI is not on the FPGA target, the Open FPGA VI Reference function downloads the compiled FPGA VI to the FPGA target. If you select Open and Run from the shortcut menu, the FPGA VI starts running if it is not already running."

This sounds to me as just downloading a bitfile would not help as the Open FPGA VI reference will overwrite it if it does not match the one compiled in. Maybe using the build specification approach is really the best.

Thank you!