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Hi all,


I need your opinion about a problem.
I need to reproduce a data file on a cRIO. Typically the file is made of recorded data from the field with at least 2 columns : time and value.  I would use a cRIO to reproduce the file and stimulate my target (device under test) with the same condition of the equipment on the filed.

The idea is :
1)  trasfer the file on cRIO file system and open it.
2) read the data from the file with Read Delimited Spreadsheet and save the value in an array
3) read the array, row-by-row, with an auto-indexed tunel loop
4) Inside the loop send the data, organized into a cluster, to cRIO FPGA via RT-FIFO
5) On FPGA keep in listen on the RT-read and get the message when ready

Someone has experience in this case? Any suggestion?


Thanks

 

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5 hours ago, Ratataplam said:

3) read the array, row-by-row, with an auto-indexed tunel loop

4) Inside the loop send the data, organized into a cluster, to cRIO FPGA via RT-FIFO
5) On FPGA keep in listen on the RT-read and get the message when ready

Not sure if this was a typo, but RT-FIFOs are between loops on the RT side. You would use a Host-to-Target FPGA FIFO to pass data down to the FPGA for output. These fifo types do not support clusters, so you'd have to develop your own scheme for passing data down. This may be as simple as sending values in chunks of N, but you do have to watch out for overflows.

If you are sending data from RT to FPGA there is a likelihood of underflow, depending on the output rate. You would probably wish to load all your file data into the fifo first and then tell the FPGA to start reading. This all depends of course on how much data you have. If you have 10 minutes of data at a rate of 1 Hz, this is overkill but would still work. If you have 10 minutes of data at 100 kHz, then you likely won't have enough memory, so you'll want to preload the FIFO and then feed data as fast as you can.

 

You'll also want to keep in mind the signals side of this. I'm not great in this area, but I would imagine that you are attempting to replicate a continuous signal, you'll want to output as fast as possible to reduce frequency spikes as the output changes.

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14 hours ago, smithd said:

Not sure if this was a typo, but RT-FIFOs are between loops on the RT side. You would use a Host-to-Target FPGA FIFO to pass data down to the FPGA for output. These fifo types do not support clusters, so you'd have to develop your own scheme for passing data down. This may be as simple as sending values in chunks of N, but you do have to watch out for overflows.

If you are sending data from RT to FPGA there is a likelihood of underflow, depending on the output rate. You would probably wish to load all your file data into the fifo first and then tell the FPGA to start reading. This all depends of course on how much data you have. If you have 10 minutes of data at a rate of 1 Hz, this is overkill but would still work. If you have 10 minutes of data at 100 kHz, then you likely won't have enough memory, so you'll want to preload the FIFO and then feed data as fast as you can.

 

You'll also want to keep in mind the signals side of this. I'm not great in this area, but I would imagine that you are attempting to replicate a continuous signal, you'll want to output as fast as possible to reduce frequency spikes as the output changes. 

thanks a lot, your suggestions have avoid several attempt

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Yes, what you're doing is super common. It might be worthwhile to use the TDMS file format instead of a spreadsheet file. It's a very easy format for recording and playing back data.

I'm a little curious why you're using a CRIO. It's not a bad choice but something a CDAQ could be simpler.

Edited by infinitenothing

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