myRIO ADC, max sample rate

[foxman]

Hello colleagues! I have a next task: It is necessary to get analog data from 4 ADC channels of myRIO with max sample rate. As we know myRIO has max rate 500 kS/s for all channels. So we have 125 kS/s per channel (500/4). It's good. A question in the next: how I can send data from FPGA target to RT in this case? I have tried to use large size FIFO buffer (target to host) but got compilation error. As I understood FIFO buffer doesn't use external memory for data storage and uses FPGA resources. The next step I think to use max available size buffer and interrupt on host when buffer is full, but in this case I will probably get skips in data stream, because interrupt requires about 400 us. Can I read data from buffer on RT level with invoke node in parallel data writing on FPGA target? Will there be an overlay in this case? And where I can read any info about fast data logging with RIO platform?

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Thank you for your help.

Edited September 4, 2019 by Вадим Ладик

[Tim_S]

The DMA FIFO is what you're looking for with the data transfer.

Edited September 4, 2019 by Tim_S

[foxman]

5 minutes ago, Tim_S said:

The DMA FIFO is what you're looking for.

Thank you for link. Yes, sure, I'm using FIFO, but I don't know as I can realize correct synchronization without data skips on fast speed.

[Tim_S]

I've gotten a test bench of 1 MS/sec of 32-bit data (24-bits plus 8-bits channel identifier) across FPGA->RT->Windows using DMA channel to RT FIFO to TCP and let it run overnight without drop of any data. Buffer was set to maximum size of U32. Now that was with a cRIO rather than a myRIO. 

Are you using NI's recommendations for best practices? Particularly the one where you check for available (request 0 samples) and then read all is a good way to read on the RT side. If you wait until the buffer is full then the FPGA can (and almost certainly will) overwrite before host side can service an interrupt.

[Neil Pate]

The DMA FIFO is silly fast if configured correctly. I have used it in a VST to losslessly stream (continuously for tens of hours) something on the order of several GB/s to disk. That was using PXI, and not myRIO though.

Don't forget, the host (RT) is actually the place where data gets buffered, and this is where you can make a nice big buffer. You don't really need a big buffer on the FPGA, you just need to make sure you read from the host buffer fast enough. As Tim_S said, do the trick where you read zero samples, this will return no data but will give you the number of samples actually available.

[foxman]

On 9/4/2019 at 7:03 PM, Tim_S said:

I've gotten a test bench of 1 MS/sec of 32-bit data (24-bits plus 8-bits channel identifier) across FPGA->RT->Windows using DMA channel to RT FIFO to TCP and let it run overnight without drop of any data. Buffer was set to maximum size of U32. Now that was with a cRIO rather than a myRIO. 

Are you using NI's recommendations for best practices? Particularly the one where you check for available (request 0 samples) and then read all is a good way to read on the RT side. If you wait until the buffer is full then the FPGA can (and almost certainly will) overwrite before host side can service an interrupt.

 

19 hours ago, Neil Pate said:

The DMA FIFO is silly fast if configured correctly. I have used it in a VST to losslessly stream (continuously for tens of hours) something on the order of several GB/s to disk. That was using PXI, and not myRIO though.

Don't forget, the host (RT) is actually the place where data gets buffered, and this is where you can make a nice big buffer. You don't really need a big buffer on the FPGA, you just need to make sure you read from the host buffer fast enough. As Tim_S said, do the trick where you read zero samples, this will return no data but will give you the number of samples actually available.

 

Thank you for your help! I have gotten a necessary result with max sample rate (500 kHz).