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Tim_S

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About Tim_S

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  • Birthday 10/17/1974

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    LabVIEW 2015
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    1994

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  1. Not familiar enough with Linux or ZeroMQ to give a specific answer, but thinking this through... Segmentation fault is the program trying to access memory it's not supposed to. Certainly been able to do that on Windows, so I don't see why can't do the same with Linux. Typically get that when working with drivers, which ZeroMQ would qualify as. Could be something like passing a pointer that is or becomes invalid, or trying to access memory that has been freed up.
  2. The site is doing a sales pitch on it's front page. That's fine all sites do that. I'm already a customer so I go to the NI site for 1) product information, 2) support, or 3) downloads. It took me poking about a bit to find what was looking for as the navigation feels almost hidden up top. Now that I've got an idea of how the layout has changed I think I'm OK and it might be more navigable. Just got to ignore everything past the top inch of main page and all should be good.
  3. Something the "supplied cables" reminded me of is that APC UPS (at least the ones I've been using) use a non-standard pinout on the DB9 for serial communication. The UPS comes with a cable with the correct pinout on each end. Any chance that's what's causing grief?
  4. Should HID start testing your sanity... Tripplite has a relay card
  5. Your Keyence representative should be able to help if you can't get it from the website. I've been in contact with multiple over the last few weeks, so I expect you would be able to get a response today.
  6. Don't know if this will work with your design, but... I have a similar situation of class reference to itself. The code is the base object for plugins and gets compiled into a packed library. The class has a vit inside of it that the child uses to create a version that it sets in a property. The property is strictly typed to the vit and gets called by the parent. To make this work I had to put a control of the reference in the library the parent class is in. This is the way I was able to get around a reference to a class within itself.
  7. The only time I consistently use Defer Panel Updates is with a TreeView control, which is slow to update the display (particularly when creating hundreds of rows). Another strategy is to check for data change to see if an update is needed. But, really, it depends on what you're doing. A configuration/editing screen is driven by user actions, so one event trips multiple updates to the UI and Defer Panel Updates can be useful. A screen showing periodic data may update each message with no issues, or checks if anything needs to be updated and when it does may need to defer updates to do so q
  8. Looks like all the PYNQ boards are programmable in Python. There was a question on NI Community about this.
  9. Working fine in 2015 (latest I've got installed).
  10. I don't have the vision addon installed, so can't point you to a specific VI. I recall there being an example that performed a histogram of the colors (in RGB?). You may need to open up various vision examples as it might not specifically state it was a histogram example.
  11. I think you're looking for annotations.
  12. Stopped having that issue once went to using win32 calls to make window frontmost and always on top (which has created new issues). Seems like would either hide the window while the file dialog was running or make the VI not modal while the file dialog was called.
  13. Fortran 77 still was taught in at least one college in 1993 on green-and-black and amber-and-black terminals. Was even a mandatory class for freshmen.
  14. I've gotten a test bench of 1 MS/sec of 32-bit data (24-bits plus 8-bits channel identifier) across FPGA->RT->Windows using DMA channel to RT FIFO to TCP and let it run overnight without drop of any data. Buffer was set to maximum size of U32. Now that was with a cRIO rather than a myRIO. Are you using NI's recommendations for best practices? Particularly the one where you check for available (request 0 samples) and then read all is a good way to read on the RT side. If you wait until the buffer is full then the FPGA can (and almost certainly will) overwrite before host side can se
  15. The DMA FIFO is what you're looking for with the data transfer.
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