Are FPGA interface nodes supported in class members?

[Jeffrey Habets]

I would like to encapsulate my FPGA access in a class, but it seems LV can't handle it. If I have one (or more) FPGA interface nodes in one of my methods, save and close the project and open it up again, LV crashes in exec.cpp line 1704.

I reported the problem to NI and am waiting for their response, but in the meantime I'm curious if someone else has bumped into this problem. I'm using LV8.6.

[LAVA 1.0 Content]

QUOTE (Jeffrey Habets @ Jan 3 2009, 04:28 PM)

I would like to encapsulate my FPGA access in a class, but it seems LV can't handle it. If I have one (or more) FPGA interface nodes in one of my methods, save and close the project and open it up again, LV crashes in exec.cpp line 1704.

I reported the problem to NI and am waiting for their response, but in the meantime I'm curious if someone else has bumped into this problem. I'm using LV8.6.

Jeffrey,

I had not tried this before, but decided to give it a whirl as I see LV classes being a great interface tool for the FPGA. I put together a simple class to talk to my FPGA, but did not run into the problem you described.

I have attached my project files for reference. Can you give these a try and let me know what happens?

http://lavag.org/old_files/post-3370-1231200448.zip'>Download File:post-3370-1231200448.zip

[Jeffrey Habets]

QUOTE (LV_FPGA_SE @ Jan 6 2009, 01:08 AM)

I had not tried this before, but decided to give it a whirl as I see LV classes being a great interface tool for the FPGA. I put together a simple class to talk to my FPGA, but did not run into the problem you described.

I have attached my project files for reference. Can you give these a try and let me know what happens?

Download File:post-3370-1231200448.zip

Thanks for testing this. I tried your project, and it loads fine here.. No problem.

So it seems my problem is probably not (only) class-related. Maybe it has also to do with the kind of FPGA-target configuration, I don't know.

I've attached the stripped-down project that reproduces the problem. This is also the project send to the NI AE and now under investigation as CAR#: 139277.

Note that my classes are GOOP3 (Endevo) which is basically a LV native class with some extra. The problem isn't in the GOOP3 framework for sure, since I can also reproduce it with a LV native class in this same project.

The project as attached will open without a problem because the FPGA interface nodes are commented out. To reproduce the problem, open FPGA0_DAQ.lvclass:FPGA0_DAQ_Create.vi (under Hardware) and enable the stuff that is now disabled. Save the VI and project, then close and re-open the project.

Download File:post-906-1231252734.zip

[Jeffrey Habets]

The problem will be resolved in a next LabVIEW release..

NI Offered me two possible workarounds of which I used the second one and this works for me:

1. Set resource\Framework\Providers\lvrio\crio.llb\_nicrio_getModuleXML.vi and _nicrio_getModuleXMLForRSI.vi to non-reentrant. Since these are password-protected VI's that's not really an option for normal users.
   
2. Configure the Open FPGA Reference node to use the bitfile instead of the FPGA VI.