Method of interaction between FPGA loops

[Tim_S]

I've been getting ready to design some code for a cRIO system and have a general architecture question. I can see where my application will be broken into separate loops within the FPGA. Some of these loops will interact with each other. I'm anticipating that not all of the loops will reside within the same VI. What have people found to be the "best" way to interact between loops within a FPGA? Functional globals seem undesirable when dealing with single-cycle loops. Queues and notifiers are not available. FPGA Memory appears to be a good choice, though it has special considerations for single-cycle loops and cannot be used with multiple clock domains. FIFOs appear to be best suited for communication between the RT and FPGA. Do global variables become a preferred choice?

An example of what I'm thinking is this: One loop performs an RPM calculation from a digital tachometer coming into a digital input. A second loop measures 7 analog inputs and sends the inputs as well as the speed to the cRIO's RT host. There is, of course, more complication that that, but that is the basics of the FPGA application.

Thanks.

Tim

[hooovahh]

I haven't worked with FPGA much but the only way I've ever been able to accomplish what you want is using local variables. "In FPGA local variables are your friend" - My boss

When you want one loop to send some data to another loop you can set a boolean which the second loop is watching. When that boolean is true you can have the second loop grab some data from a local variable. It's not as easy to follow as the state machines we're use to, but it works.

Take a look at this example (a poorly thought out one, but one none the less)

I realized after making this example it is a poor design of an alarm system. If an alarm happens when the system is handling alarms, it will be cleared. Also Arrays in FPGA are very costly in number of gates and they should be avoided when ever possible. But in any case I hope you get the idea on how I some times pass data from one loop to another.

[ned]

The FPGA module offers two types of FIFOs - FPGA FIFOs (both "target-scoped" and "VI-scoped"), and DMA FIFOs. The former are for transferring data between loops on the FPGA, the latter are for transferring data between the FPGA and the host system. The FPGA FIFOs are an efficient way to transfer data between loops, as is FPGA memory in a single-reader single-writer situation. Expect a learning curve and plan to rewrite your initial attempt a few times - the FPGA module looks like LabVIEW but requires you to think about how your code is executing at a lower level to take full advantage of it.

[Adrenaline]

Global Variables work very well for transfering data within the FPGA. You want to stay away from Local Variables becuase those require a Front Panel control, more FPGA space is required to work with the RT host. The biggest issue you will run into is race conditions with using Global Variables if you have more than a one loop writing to the variable.

Arrays are okay on the FPGA as long as you keep the element count low. An array of 4x8bit integers will take the same fabric as a 32bit integer.

I have not used FGPA memory becuase the latency was not acceptable in my application.

One thing to be aware, try and minimize FPGA I/O nodes. They take a lot of space on the FPGA, try and use less than 6 "nodes" with any number of elements.

I have 32 loops that each set a digital output seperately. I had to use a global boolean for each loop; then have another loop read all 32 global booleans and build an array to output to the digital output card. Because using 32 I/O nodes didn't fit on the FPGA.

[Tim_S]

I really appreciate the responses and advice. Thanks to everyone.

This has definitely been a challenge in thinking how to structure the application for best performance where there the resources are very limited. At this point I've created three VIs. The first contains the other two. The second performs the clocking, start DAQ, stop DAQ, and passing of data from a global variable (32 element array of U32) over a FIFO to the RT portion. The third VI writes to the global array of U32 from a FPGA I/O node and speed calculations off encoders going to digital inputs. Populating the global with the data and pulling it out at the desired sampling rate seemed the best idea. That was until something started nagging me from, uhm... a decade or so back... about signals theory and sampling. I'm pretty sure I've held onto that text book... time to dust it off!