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The hallmark of an experienced LabVIEW developer is the usage of their or others templates which prevent the ubiquitous blank block diagram symptom where time is wasted doing the same thing that they have done before. Attached and linked you will find the TLB` (prime) template which, after a little learning what the parts are, can take you from zero to 60 in no time the next time you need to create a Top-Level application or interface. This template can be used from the ultra simple UI to a fairly complex application. Many questions and comments have been made about the original design (TLB) which is located here http://lavag.org/topic/14164-discuss-tlb-top-level-baseline/ This reason for the update in this design is detailed in the presentation "Rebirth of the LabVIEW State Machine" which is accessible here http://lavag.org/topic/16091-ni-week-2012-videos/page__view__findpost__p__97844 Installing and Creating http://screencast.com/t/vtlFgLhQqT Review of Examples http://screencast.com/t/XLIN0yjS Structure of Code http://screencast.com/t/5RtMhPVujS Basic Flow of Operational Code http://screencast.com/t/1QGFRRuSf0nT Adding a control to the system http://screencast.com/t/IJTxEQ28 Adding an action to the system http://screencast.com/t/5984lGlMjM <More to come soon> QSM Evolution.zip Code used in presentation video detailing why the typical QMH is fraught with issues that we have all run into Credit to Daklu for it's creation and sharing ni_tool_tlb`-1.2.0.23.vip Most up to date version of TLB` Rebirth of the LabVIEW State Machine.pptx TLB` Application Template.vipc

A lot of traditional good LabVIEW style doesn't apply to FPGA. You want to avoid arbitration - multiple loops all trying to access the same resource, such as a functional global. Also, to maximize FPGA space available for your logic, you want to minimize the amount of space used for data storage by using FIFOs or memory blocks instead of global variables or functional globals. A memory block acts a lot like a global variable in practice, but it is an efficient way to store and share data on the FPGA, and you can avoid arbitration if you have only one location where you read and one location where you write. Similarly, you can choose to have your FIFOs implemented in memory. Note that there's a difference between a DMA FIFO, which passes data between the FPGA and host, and a FIFO that only passes data around the FPGA. I try to break up my FPGA code into tasks that are easily separable, because the FPGA is really good at doing work in parallel. For sending large numbers of parameters from the host to the FPGA without using a lot of front panel controls, I'd put three controls on the front panel: a data value, an index, and a boolean indicating that the value has been read (you could also use an interrupt). I'd then have a loop dedicated to monitoring the boolean; whenever it's true, write the data value to the specified index, then set the boolean to false. The host sets the value and index, then the boolean, and waits until the boolean has cleared before sending the next parameter. Another loop in the FPGA code reads from the same memory block as necessary to do calculations.