I have a system that composed of 1- NI-cRIO9014 2- Chassis (cRIO-9104) 3- Three Mods. NI9215 I use this system to capture 12 analog signals. What is the relation between sampling frequency defined by time delay in fpga.vi and the Requested number of Elements defined in FIFO?. When I use a time delay of 40us and Requested number of Elements 8191, it produces wrong data. When I use a time delay of 40us and Requested number of Elements 65535, it produces correct data.
I have a system that composed of 1- NI-cRIO9014 2- Chassis (cRIO-9104) 3- Three Mods. NI9215 The following are properties of my current FPGA Target Class: cRIO-9104 FPGA Device Information: Family: Virtex-II Type: xc2v3000 Speed Grade: -4 Package: fg676 Compiler Information: Version: Xilinx 10.1 Xilinx Options in Build Specifications: Supported Host Computer/FPGA Communication: Programmatic FPGA Interface Communication: Supported Interactive Front Panel Communication: Supported Number of Logical Interrupts: 32 DMA: Number of DMA Channels: 3 Multi-Element Access on Target: Not supported Peer-to-Peer Streaming: Not supported Type: Target to Host - DMA Control logic: Slice Fabric I am reading 12 Analog signals, I do not know what is the maximum value for Requested Number of Elements I can use? The General page help says a size of 2^M-1, What is M?