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I have a system that composed of 1- NI-cRIO9014 2- Chassis (cRIO-9104) 3- Three Mods. NI9215 I use this system to capture 12 analog signals. What is the relation between sampling frequency defined by time delay in fpga.vi and the Requested number of Elements defined in FIFO?. When I use a time delay of 40us and Requested number of Elements 8191, it produces wrong data. When I use a time delay of 40us and Requested number of Elements 65535, it produces correct data.