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Showing results for tags 'labview fpga'.
Found 3 results
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I posted This on the Idea exchange a few days ago. I have been wondering why no-one sees the need for constant generation at compile time. I think this would be especially useful in FPGA, but also for constants that need data from the build environment. Perhaps there is just a better way of doing these types of operations? Let me know what you think? -
Bonjour, Je recherche pour une mission chez un équipementier aéronautique en région parisienne un(e) ingénieur(e) LabVIEW expérimenté(e). Compétences souhaitées : LabVIEW RT et LabVIEW FPGA. Une connaissance des bus de communication CAN, ARINC et AFDX ainsi que de TestStand serait fortement appreciée. Disponibilité ASAP Contactez-moi en MP ou par Mail : jlinisa@linsys-technologies.fr Jean LINISA Certified LabVIEW Architect Consultant
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I am having trouble realising an FIR filter in Spartan 3E XUP board. I have succesfully compiled the FPGA VI generated from "Generate IP" (However, IP Builder sub menu is not existing this board in Project explorer as given in FPGA IP bulider tutorial). The FPGA Vi wil be running in SCTL receiving FXP data elements. But an array of data is required for the filtering to happen. How to do this without DMA FIFO as the board supports only Target scoped FIFO?
