Closed Loop Control System Could Go Unstable Due To Noisy Feedback

[KWaris]

I am nearly there. I designed an FPGA based PID closed loop control system, did all the scaling for the raw volts signals to make sense to my customer. Its works beautifully well as long as we see it working as a machine. But as soon as we put a 10kHZ datalogger to see the feedback and controller output, we start seeing an unstable control system. By bit of investigation, we found that putting this unstable controller output to the actuator unit could damage it.

The cause of this unstability is the noise on the Temposonic Linear LVDT. I can see continuous fluctation when at position zero from -0.02 to 0.02. If I plot this voltage this draws into a sine wave. Consequently my controller output is a continous unstable signal.

I believe I have done my bit as a Labview programmer working on the application. I however unfortunately hold the title Control/Instrumentation Engineer and customer is looking at me and I have given all the theories I had learnt in the university from the basic PID control theory, mathematical model, laplace transform to fuzzy pi controller. But at the end of the day I have got to fix it. However I dont seem to get to the bottom of this noise issue and eradicate it.

I am seeing this noise pattern on all the analogue. Filter in FPGA doesn't seem to work. Wiring and screening all ok. Cant afford averaging and mean techniques for the control system as the system must respond for a very tiny change in distance.

I still hope people in the world had designed fantastic control application using NI. I was just reading an article where somebody managed to hold and control the position of a vertical steel ball in space based on closed loop control system.

I am attaching my FPGA vi here which I have used to achieve a very small value of integral gain. It works a treat. I think I need advice on designing some software/hardware filter here.

Kind Regards

Austin

[ShaunR]

I can see continuous fluctation when at position zero from -0.02 to 0.02. If I plot this voltage this draws into a sine wave. Consequently my controller output is a continous unstable signal.

What frequency is the sine wave. 50Hz? What is the +-0,02 in comparison to the range (+-5v sensor?)

Does your PID controller implementation have a dead band?

[asbo]

But as soon as we put a 10kHZ datalogger to see the feedback and controller output

Hardware or software datalogger? Are you hooking leads up somewhere or is it built into the existing FPGA application?

[Zyga]

HI.

I had similar problen in my high-current measure system. And I haven't solved it.. The noise was present when, circut was open, and there weren't any current. What is curious, the noise amplitude was on the same level as yours. I circumvented it simply, by not not measuring current when relay was open, and manually putting 0 value to calculations..

[KWaris]

I haven't had a chance today to study in detail the frequency but it looks to me a 50 HZ signal. The signal range is +- 10V. Please find attached my PID vi. It doesn't have the deadband. I have modified NI standard express vi to achieve very low integral. My system wont respond to higher integrals.

This datalogger is built into the same FPGA. I have also used an additional analogue output module and mounted on the electrical console some BNC connectors for my customer to use the external datalogger.

Many Thanks

PID.vi

[ShaunR]

Well. As you know. It is the integral term that dampens ringing and overshoot.

+-0.02v out of +-10V is 0.2% of FSD and I expect that is within the spec of the device. So the choices as I see it in the absence of being able to increase the integral and without getting into process modelling are:

1. Apply a 50-60Hz band-stop filter on the input (try and reduce the amplitude of the mains signal).

2. Apply a median filter to the Derivative term (reduce the feedback sensitivity to noise)

3. Introduce a dead-band (turn off control when within set limits-good for mechanical systems)

4. All or a combination of the above.

Edited August 13, 2012 by ShaunR

[KWaris]

'It is the integral term that dampens ringing and overshoot'

When I started closed loop control, I started with the belief that

P - controls the speed of the controller

I - reduces the steady state error

D - reduces the overshoot

However in reality, after setting it all up, I found:

When P was 1 -5, the system will overshoot and oscillate around the setpoint, Increasing it to 40 in my attached vi and giving it a small integral of 0.00000000003 reduced all

oscillations and overshoot. And controller holds the output once the target setpoint is reached. Spot On, No issues. Derivative do nothing. ( I am slightly disappointed why things sometimes

dont work as described in the textbooks).

I cant see the band stop filter on the FPGA, is there a vi somewhere I can download? Alternatively, I could use the combination of low pass and high pass filter to achieve this?

Please advise

Many thanks

Ok. Lets put in a 50 - 60 Hz filter on the input. How do we do it?

In my FPGA, I have Analogue input node which is dragged from the project explorer onto the block diagram of FPGA. There is only a butterworth filter available on the FPGA and wiring

the Analogue input to the input of the filter and configuring the filter had not given my satisfactory results in the past. I must admit I did not think hard the first time I tried it and just wired

the inputs hoping things will work. Have you guys used this filter and does it work?

[Mellroth]

I am attaching my FPGA vi here which I have used to achieve a very small value of integral gain. It works a treat. I think I need advice on designing some software/hardware filter here.

I have not found your FPGA.vi so I cannot say anything about that, but in a RealTime project long time ago we implemented simulation of LVDT and RVDT signals on a PXI FPGA board.

The exitation signal was in this case more than noisy, so it had to be filtered.

Our solution was to use a PID controlled PLL, with the exitation signal averaged X number of samples.

This solution meant that the averaging of the input signal had no effect, and that the DUT could not detect any phase shift between the exitation and the RVDT signals (phase difference had to be less than 0.1 degrees if I remember correctly).

/J

[ShaunR]

There are filter examples shipped with the FPGA (look for "notch filter") and there are IPs that you can download from NI that also give you more filters such as the median filter. You can even create your own IP using the IP wizard in the project manager if push comes to shove, but I've never used it (I'm lazy like that)

It is not unusual for the derivative term to do nothing in some systems. With such a small integral, it is arguable whether you really need a PI controller even.(P only with deadband for example). However. It's "software", so what the heck eh? It works and that's the main point.

Edited August 14, 2012 by ShaunR