TDF team is proud to propose for free download the scikit-learn library adapted for LabVIEW in open source.
LabVIEW developer can now use our library for free as simple and efficient tools for predictive data analysis, accessible to everybody, and reusable in various contexts.
It features various classification, regression and clustering algorithms including support vector machines, random forests, gradient boosting, k-means and DBSCAN, and is designed to interoperate with the Python numerical and scientific libraries NumPy and SciPy from the famous scikit-learn Python library.
Coming soon, our team is working on the « HAIBAL Project », deep learning library written in native LabVIEW, full compatible CUDA and NI FPGA.
But why deprive ourselves of the power of ALL the FPGA boards ? No reason, that's why we are working on our own compilator to make HAIBAL full compatible with all Xilinx and Intel Altera FPGA boards.
HAIBAL will propose more than 100 different layers, 22 initialisators, 15 activation type, 7 optimizors, 17 looses.
As we like AI Facebook and Google products, we will of course make HAIBAL natively full compatible with PyTorch and Keras.
Sources are available now on our GitHub for free : https://www.technologies-france.com/?page_id=487
I'm a beginner in labview, and now test cRIO about two weeks. I still can not solve the problem. I attach my test project for explanation.
I want to realize that , for example, with time sequence t1, t2, t3, t4, DO outputs T, F, T, F, AO1 outputs A1, A2, A3, A4, AO2 outputs B1, B2, B3, B4, and the delay of AO1 and AO2 should as small as possible(AO1 and AO2 may comes from difference modules).
I search in Google, NI forum, and decide to use for loop and loop timer in FPGA.
The reason as follow:
1. To realize the specific time interval, I can use Wait and Loop timer. But in "FPGA 0--Test DO.vi", it can't not realize specific time interval by several us's error(maybe large). And to complete once of while loop, it needs 134us. I can't explain that it can realize time interval below 134us, even I acturally realize a delay of 10us, but the input is not acturally 10us, so it's not accurate.
And by NI example, I use the Loop timer.
2. In "FPGA 1--Test DO and AO.vi", I find that the loop timer helps me to realize accurate time interval, however, it ignore the first time interval. Such as, t1, t2, t3, t4, with disired output A1, A2, A3, A4. It goes A1(t2), A2(t3), A3(t4), A4(t1). And in "FPGA 2--Test DO and AO.vi", it has same problem. DO0 and AO1 goes A1(t2), A2(t3), A3(t4), A4(t1). And AO0 is always ahead of DO of t1.
The people of NI forum advice that I should put AO0 and AO1 into one FPGA/IO node and use SCTL. But up to now, I don't find any example about it(Google or NI forum, maybe it's primary). Mainly that AO0 and AO1 must go with different timeline, the dimension of input array is different. Can anyone offer advice for me?
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I would like to build a model using image data and NI-cRIO-9063 and NI 9264 for voltage control.
for image, I made a script in python using OpenCV libraries that detecting some points . For voltage control, I use cRIO-9063 with NI 9264 voltage controller.
My question is, I am new in LabVIEW and I don't have any idea how can I make a loop for voltage control in python. Is there any library available in python that directly connect cRIO and NI 9264 devices? if not then how can I combine my image data(which is in python) with cRIO device? I need argent help.
By Makrem Amara
I am working on a machine vision project with LabVIEW.
The camera will locate some parts and send their coordinates via TCP/IP
and I created a client also with LabVIEW to display these coordinates here is how the communication going.
First, if the camera detects something then msg will be sent to the client to inform him.
then if msg was received correctly client responds with another msg to request the coordinates.
at last, the server sends the coordinates to the client.
here I faced some problems
1- the msg sent are with variable length ("x=0,y=0,Rz=0"==> "x=225,y=255,Rz=5" ==> "x=225,y=255,Rz=90" length vary between 16 and 22 ) with the constant "byte to read " it will not display the full msg.
2-the client works fine but at a certain time, it shows errors like ("LabVIEW: (Hex 0x80) Open connection limit exceeded";;;;;; "LabVIEW: (Hex 0x42) The network connection was closed by the peer. If you are using the Open VI Reference function on a remote VI Server connection, verify that the machine is allowed access by selecting Tools>>Options>>VI Server on the server side"