"Required" terminals are more efficient?

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QUOTE(Aristos Queue @ Nov 7 2007, 10:53 PM)

I DISBELIEVE....

I undestand.

I did not beleive it at first either.

I understand that I will have to justify my previous assertion.

I will post numbers and images of code as soon as I can.

Ben

[Tomi Maila]

I ran some tests with this. I didn't notice any difference in the speed of different connector panes. However I noticed that parallel nodes or structures on a block diagram run with different speeds consistently i.e. in a non-random manner. So take care where you place your most time-critical loop

Download File:post-4014-1194527735.zip for LV 8.5

Tomi

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In the future maybe I should keep these tidbit secret.

To be able to measure the difference between calling a sub-VI with spare terminals and a sub-VI with no spares, was no easy task and has a strong resemblance to creating a topographical map of your naval.

To conduct this experiment we used a PXI-1042 chasis with the following modules.

PXI-8106 Dual core

PXI-6653 Timing control

PXI-6608 Counter

We used the oscillator of the of the 6653 to drive the DDS and prouduce a 80MHz reference clock. The 80 MHz clock was then routed to Clk Out and then cabled back in to the Clk In of the 6653. The Clk In was then routed to the PXI balckplanes star lines.

The 6608 was then set up to count based on the clock from the PXI backplane.

In other testing (not shown here) we measured how often we can read from the counter and those measurements showed that the CPU could read from the counter every 4.4 microseconds.

We then constructed the diagrams shown below (Exact = only as many connections on icon connector as required. Spare = extra un-used terminals)

A timed loop was used to "hold the test code" and to allow us to specify in which of the two CPU's the code runs. (Note: this was done because overhead routines apparently run on CPU "0" and will interfere with the mesurements. This "inference" manifests itself as a high standard deviation in the loop times "jitter").

The test code begins by allocating two buffers who's size is the same as the "loop Iterations" Control which was set to "1" for these tests. (Note: "Show buffer allocations indicated that the buffers were NOT being copied and the sub-VI were working in the buffers created by the "init arrays".)

After the allocation of the buffers, the timing scheme described earlier was configured and started.

The code the repeatedly calls the sub-VI's which are simple No-OP for loops that iterate the number of times indicated by "Loop iterations", again "1" and return.

After calling the sub-VI the specified number of times the couter was again read.

The difference between the counter values (scaled as ms as indicated by the clock rate) was then used to determine how long it took to cal the sub-VI the specified number of times.

Repeated testing showed that the sub-VI calls to a sub-VI with only as many connectors as we needed were consistantly faster.

The difference was approximaly 8 nanoseconds.

If you see anything I may have missed please chime in!

Q:

How can I explain the differnce in behaviour between the two methods if its NOT due to the extra terminals?

Ben

"Naval surveyor"

PS: We still have NOT noticed a difference in calling a sub-VI who's inputs are marked as "requied".

[Aristos Queue]

I'm going to flag this whole discussion for the LV performance team and see if there's any feedback. They're a bit busy at the moment, so it may be a while before a response.

[crelf]

QUOTE(neB @ Nov 10 2007, 01:01 AM)

In the future maybe I should keep these tidbit secret.

no No NO! If you do, you will be soundly spanked! (unless you like that sort of thing, and then you will be tied to a chair while forced to watch someone else be spanked (unless you like that sort of thing, and then...))

Ben: can you please upload the VIs you used to do the benchmarking ro keep all of the thread items together?

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QUOTE(i2dx2 @ Nov 9 2007, 11:31 AM)

...Ben: can you please upload the VIs you used to do the benchmarking ro keep all of the thread items together?

Since I have a customer is paying for this work as part of a big project and they have not received the results yet, it would be wrong to post the code now.

I am concidering writting a Nugget to document my adventures in performance-land after the data and systems have been delivered.

Ben

[Yair]

QUOTE(neB @ Nov 9 2007, 05:01 PM)

Let me guess - you wrote "naval", right?

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QUOTE(Yen @ Nov 10 2007, 11:33 AM)

Let me guess - you wrote "naval", right?

That would be an excellent guess if I knew how to spell one vs the other and could tell the difference. my wife pointed out the two words were spelled differently. :headbang:

again!

Ben

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QUOTE(neB @ Nov 11 2007, 12:20 AM)

Since I have a customer is paying for this work as part of a big project and they have not received the results yet, it would be wrong to post the code now.

Why? I'm not asking you to upload your customer's code - just a snippet (something simple created from scratch would work) that demonstrates the issue.