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Well references and error wires could default to shift register terminals when wired into the loop? Much like arrays default to auto-indexing. This would also be useful for counteracting the auto-indexing of references and errors when exiting the loop.

Hi Alex, In your FPGA Control Loop, you have the error wired to a shift register on the while loop. In case of an error, you are enqueuing an error command, but are also passing the error from that iteration f the while loop to the next through the shift register. So in the next iteration, the Dequeue Element sees the error wired in. It does not execute to pass on the "error" message you enqueued, instead it passes the control with an empty deueued element, which of course will give you an empty string. That is why the loop goes to the default typo handling case. Fix: either do not use a shift register for error on the while loop, or clear error in the "Error" case, where you are enqueuing the "error" message, so that the Dequeue element can work properly and see this message.

Indeed, I do the same. My only real rule is to "never" pass event registration refnums to subVIs due to the static typing. The event registration always stays in the VI that has the event structure using the registration, but I impose no restriction on where these are relative to the actual event source(s).

For inserting an object's UI into a subpanel, I have used the reverse approach successfully - I have a DD VI that accepts a reference to a subpanel called something like "Insert UI", then its up to the individual class to decide what VI gets inserted and give the opportunity for the class to do any housekeeping before actually displaying its UI to a user. Here's a pic: