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The blue-ish or green property or invoke nodes indicate scripting. Saying "Scripting" is not available in the run-time engine is an absolute that is a little fuzzy at times. Some functions are indeed only available at run-time. Like the Save Instrument invoke node. From a build EXE you don't have the ability to save a VI, so this function won't work in the run-time engine. To know if your function specifically is supported in the run-time you can open the context help, and over over the function. It will say if it is supported in the run-time engine and real-time. If this function works in the run-time engine, then you should have no worries using it. If you would like to enable scripting, so these functions can be used, other than copying the one you have, you can enable it by going to Tools >> Options. Then under VI Server check the box that is Show VI Scripting functions. Now your property and invoke nodes will have a lot more functions.

To follow up some of my earlier questions for future readers: I used to keep copies of all VIs under both targets, but it was a pain keeping them synchronized. On top of that the classes would end up locked because it was being loaded on multiple targets. Now I keep all the RT code under one target and copy the top level VIs to the other target when I need to run the code on that target. It seems to be working quite well. Currently I have my entire FPGA code fully listed under both targets, but I'm pretty much done with that and just haven't bothered cleaning it up. It doesn't have the same problem with locking VIs so there's no motivation to mess with it right now. I suspect I could just copy the top level FPGA VIs to each target and it would work fine. Each FPGA target does maintain its own project-defined resources and build specs. I had thought all symbols were defined in the project and the built-in symbols did some magic behind the scenes. Turns out it is much simpler than that. I discovered each RT and FPGA target has its own list of conditional disable symbols. Setting symbols for each target means I don't have to remember to switch symbol values every time I run the code on a different target. The FPGA_TARGET_CLASS symbol lists the platform model, such as CRIO_9074 and SBRIO_9636. Very handy.