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PJM_labview

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Posts posted by PJM_labview

  1. I am also VERY interested in finding out if this is possible. I looked for such settings a while back but I could not find anything. Since I have to change this settings manually constantly for every VI I worked on that I did not create, having a way to do this programmatically would be very handy.

    Below is what I want to be able to do programmatically:

    From:

    post-121-1191017740.png?width=400

    To:

    post-121-1191017757.png?width=400

    Basically I hate to have to do this operation several times a day...

    PJM

  2. QUOTE(Gary Rubin @ Sep 20 2007, 11:39 AM)

    Hmmm, that does seem odd - maybe a difference in memory speed between the single-core and dual-core systems?

    This was on a PXI chassis (1031 DC). The "Brain" was upgraded from a NI PXI 8196 to a NI PXI 8106 (dual core), and I believe they took the memory from the old one and put it on the new one (2Gb Total).

    Other than these specific CBR recursive VIs, everything else run smoother and faster.

    PJM

  3. QUOTE(Gary Rubin @ Sep 20 2007, 09:39 AM)

    This sounds indicative of non-parallel dataflow. What you described sounds like each core is spending half its time waiting for the other to finish.

    If you do not see total CPU usage over 50%, then you are not actually doing anything in parallel and would not expect any better performance than a single core.

    While I would not necessary expect improved performance, I certainly would not expect worse one. But this has happened.

    You are probably correct regarding the code not doing anything in parallel though. This was a bunch of VI doing recursive CBR call.

    PJM

  4. QUOTE(Gary Rubin @ Sep 19 2007, 05:46 PM)

    I think the answer is "yes" to both. It depends on how parallel your processing is. You usually can see some increase in performance just by dropping it onto a multicore system, but you might be able to do much better by being careful with your threading and taking advantage of some of the thread priority settings.

    This is not quite that easy. In some instance your code may run faster, in other it may actually run slower. What I have noticed in LabVIEW 8.21 is that when you get a multicore the load end up spread more or less evenly between the two core, but for some reason it is "harder" to reach high processor usage. So in some situation, you may have some code that may use briefly 90% of a single core processor and take about 1s to run and the same code on the multi core will be balanced at about 50% on each core and take 2s to run.

    With LabVIEW 8.5, if you use timed loop, you can explicitly point (if you want to) at which core the code inside the timed loop run. While this feature is market at RT systems, it appear to works just fine on window. I which NI had gone one step further though and did the same thing for while loop and for loop. It would be very nice if I could right click on a while loop and select "run on core1" for example. Fortunately, it seem that you can trick LabVIEW in doing so by wrapping the code you want to run on a specific core inside a time loop (not very elegant at all, but the test I run seem to indicate this work fine).

    In conclusion, when you migrate some code from a single core to a multi core, it *may* run faster from the get go, but this is not an absolute certainty.

    PJM

  5. Here is my rule of thumb:

    Whoever open the reference shoud be in charge of closing it.

    Here is some of the rational behind this:

    • One of the main reason to proceed like this is to improve code clarity.
    • Another reason is to prevent bug. If you close the ref deeper in the hierarchy you might be tempting to branch the source wire upper in the caller to realize later the reference is no longer valid.

    Therefore, in your example the caller of the SubVI should be in charge of closing it.

    Just my 2c.

    PJM

  6. This is quite odd (With debugging off, the text ends up beeing drawn on the top of the image).

    After further investigation, it appear that this *might* be happening inside the case strucutre were the I16 is coerced to a double (see image below).

    post-121-1189408121.png?width=400

    If you drop an indicator connected to the I16 inside the case structure, everything works fine again.

    It look like this might be an implaceness optimization bug.

    PJM

  7. David

    If you were to use OpenG Pakcage file (ogp) then you could defined different versions of your librarie(s) to be installed under different LabVIEW versions. If you were to do this, then the ogp version becomes THE unique version. You do not have to worry about where or how to document the different versions included in your zip file. Unfortunately, if you have never made an ogp, this will requires a little bit of work to get started.

    Just a though.

    PJM

  8. QUOTE(tcplomp @ Sep 1 2007, 02:05 PM)

    ...A probable event driven approach to 'key down' is added...

    Ton

    You can not register event on VI which are not running (this is a pitty really). Therefore the portable event driven approach VI you attached will not help in this situation.

    PJM

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