codcoder

Promising! But I am waiting for Jake to be able to produce VI snippets. Asked for a for loop and all I got was simple ASCII art. +------------------------+ | +------------------+ | | | [ ] | 0->1->2 | | | | For Loop | | // 5 iterations | +------------------+ | | Iterations | +------------------------+

Wow, thanks! This is exactly what I was looking for!

Hi, So I have this project with a lot of vi's which are saved with block diagram windows somewhat larger than the actual block diagram. I am looking for a way to programmatically go through all these vi's and resize the block diagram window size to the size of the actual block diagram (plus some margin). Has anyone done this? I'm looking at the different properties: BDWin.Bounds, Diagram.Bounds, but I can't really make heads or tails of it.

Can you put the AI node inside a single cycle timed loop with a slower clock? On my FPGA target, 7820R, it is possible to create derived clocks with both lower and higher frequency compared to the base clock of 40 MHz. Create a derived clock of 500 kHz -- if possible -- and connect that clock to the SCTL. If the compiler doesn't complain it maybe should work?

If you have a controller in the PXI chassis it can either run LabVIEW RT (used to be a PharLaps derivate but they are now switching over to something built on Linux) or Windows. If you want the PXI system to run as an embedded system, and if you need any real-time capabilities, then LabVIEW RT is the way to go. If you don't need that I do not suggest running Windows on the controller. We have a system where we do that and unless you really don't have space for a rack computer or some other external PC I don't see any advantages. What you get is basically a more expensive computer with worse performance. Just connecting to the PXI system with an MXI link is much better (which we do in all our other systems) and if I understand you correctly that's already your idea.

I'm not sure I undestand the question. LabVIEW FPGA can handle math caluclation, although decimal numbers are a bit cumbersome, and the straight line formula is pretty straight forward to implement. Are you sure you need a LabVIEW FPGA for this? Do you have a very specific application?

Yes, exactly those signals! PXI Triggers. I don't have specific experience of the PXIe-7975R but I use the PXIe-7820R quite a lot. And on that card you can simply access the trigger lines like any other digital I/O in LabVIEW FPGA. So it would be fairly simple to use Wait on Any Edge or something like that. https://www.ni.com/docs/en-US/bundle/understand-flexrio-modular-io-fpga/page/fpga-io-method-node.html

Cannot you use one of the PXI trigger signal routing? https://www.ni.com/docs/en-US/bundle/pxie-6672-feature/page/using-pxi-triggers.html

If you a certain you already have a functional license, check the license folder and remove any old ones. Those can confuse NI License Manager. The path to that folder is c:\ProgramData\National Instruments\License Manager\License at least on my computer.

Both your links were good. I've found the second one, but the first was new to me. But you are right to assume that I'm looking for something less abstract. At least, that is what I want to create here—a cooking recipe of sorts.

Hi, (This is a repost from NI's community forum. No answers there so I'm trying my luck here 😀 ) As many of you are likely aware, TestStand is a powerful tool with numerous features and incredible flexibility. While these aspects are undoubtedly valuable, they can sometimes result in the creation of test sequences that are challenging to read. In my workplace, particularly with many newcomers learning TestStand, there's a tendency to be awestruck by its programming language-like capabilities, leading to the use of excessive loops, parameters, and if-cases where a simpler, flat sequence would suffice. Recognizing the need for clarity in test sequences, I've taken on the task of creating a style guide. The aim is to keep sequences coherent without unnecessary complexity. My question for the community is whether anyone has already developed such a guide and is willing to share it? Thank you in advance!

I've always thought LabVIEW's higher level of abstraction somewhat reduced the need for that. But I'm not proficient enough in any other language to make a fair comparision.

Interesting take but does it fly with TestStand?

Well yes from a data structure point of view it is. It would make sense to store the private cluster as the private data of the class and use a public cluster as an exposed API. But solving the same issue with a library isn't that different. It doesn't however solve the issue of connecting the public and private data in some smart way. But @LogMAN provided an interesting solutionf or that! I'll look into it!

So yes I went for "brute force". But I managed to solve it using VI scripting, i.e. automatically creating undbundle-by-name from the public cluster to bundle-by-name to the private cluster. So even if the creation process is obscure the result is easy to read by someone who knows only little LabVIEW. Which was what I was aiming for.