FPGA compilation is taking much longer than it did a few weeks ago

[Sparkette]

The last two times I tried to compile an FPGA VI it took a significantly longer time than it used to, and it never ended up compiling. I forgot what stage it got to the first time, but the second time it just stayed frozen on "Placing and routing" for a half an hour, so I cancelled it, because I figured something was wrong. It was a simple VI; similar VI's compiled in like 5 minutes or less. I hadn't compiled any FPGA VI's for a week or two in between, so I don't know what I could have done in that time that broke it.

Has anyone else had a problem like this / know how to fix it? Thanks.

[Omar Mussa]

Are you compiling it locally or via Cloud Compile?  I had that happen a few weeks ago - switched to local compile - for whatever reason it 'worked' then I switched back to Cloud Compile and it continued to work - no idea why - the code if anything is more complex than it was at that point and I'm no longer having issues (no matter where I compile).

[shoneill]

I've never had FPGA code compile in 5 minutes......  Even simply benchmark tests take upwards of 30 minutes for me.... I'm jelly.

[Rolf Kalbermatter]

I've never had FPGA code compile in 5 minutes......  Even simply benchmark tests take upwards of 30 minutes for me.... I'm jelly.

 

What memory do you have in your machine? For the FPGA compiler it REALLY makes a difference if you can throw more memory at it.

[shoneill]

8 Gig, Win 7 64-bit, LV 2012 SP1

 

I have found that artificially pinning the FPGA compiler to a single core really speeds things up (up to 50% faster).

[hooovahh]

I've never tried this but here is apparently a way to decrease compile time drastically by using TurboBoost.

 

http://forums.ni.com/t5/LabVIEW-FPGA-Idea-Exchange/Multi-core-Compiling/idc-p/2301338#M297

 

This should really get more visibility.

 

As for the OP sorry no clue.

[JamesMc86]

I've seen it, actually happened in my CLED exam! but I don't have a great answer for it.

 

It's definately a compilation issue, Generally in this scenario I've either made a tiny change to force recompilation and it's enough to get around it. Other times I've had to slowly cut my VI in half to find an offending piece of code that's doing something wierd.

[Sparkette]

Now it's been stuck on Mapping; compile time is 00:25:37 and counting. It said something about a PlanAhead license expiring in -8 days; is this something that was speeding it up and now that it's expired it's taking longer? If so, can anyone recommend a good free alternative I can replace it with?

[hooovahh]

Where is it mentioning PlanAhead licensing?  Can you take a screenshot?  I've just been compiling NI FPGA for years and never seen anything with an error due to Xilinx licensing.

[Sparkette]

It's just some text in the Xilinx Log section of the compile progress window.

### Generate Xilinx IP (Generate Xilinx IP) ###

### Estimate Resources - PlanAhead (Estimate Resources - PlanAhead) ###

****** PlanAhead v14.7 (64-bit)
  **** Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.

INFO: [Common 17-78] Attempting to get a license: PlanAhead
INFO: [Common 17-290] Got license for PlanAhead
INFO: [Common 17-86] Your PlanAhead license expires in -10 day(s)
INFO: [Device 21-36] Loading parts and site information from D:/NIFPGA/programs/Xilinx14_7/PlanAhead/data/parts/arch.xml

[Jordan Kuehn]

Are you running an eval version of the FPGA module?

[ShaunR]

It's just some text in the Xilinx Log section of the compile progress window.

 

### Generate Xilinx IP (Generate Xilinx IP) ###
<snip>
INFO: [Common 17-86] Your PlanAhead license expires in -10 day(s)
INFO: [Device 21-36] Loading parts and site information from D:/NIFPGA/programs/Xilinx14_7/PlanAhead/data/parts/arch.xml

 

Xilinx14_7?

 

Did you install that or did it come with your FPGA?

Edited October 10, 2014 by ShaunR

[Sparkette]

I guess it came with my FPGA? It's a RIO Evaluation Kit from eBay.

Actually, it's more likely that it was installed when I installed the Xilinx FPGA compile tool, because LV said I needed it.

Edited October 11, 2014 by flarn2006

[Sparkette]

Okay, going into the build specification and changing the Design Strategy (in the Xilinx Options section) to Minimum Compilation Time seems to fix it.