Writing Timed Loops in FPGA Modules

[王佳]

I now need to program on a labview FPGA module and I need an efficient way to write a timed loop program. The loop program I'm currently using is shown in the diagram, and it looks like the sampling frequency is only 200k, and I'm aiming for 500k.

I know that using User Controlled I/O Sampling Acquire Faster than an I/O Node, but now one of my loops does not involve an I/O Node, and in this loop my program may be too complex to meet the 500k requirement when using the timed loop program as shown.

Is there any other way to write a timed loop?
Please provide me some help! Thanks!

[LogMAN]

I'm not familiar with FPGAs so this might not work, but there is a Timed Loop in LabVIEW: https://www.ni.com/docs/en-US/bundle/labview-api-ref/page/structures/timed-loop.html

Edit: Just noticed this note in the article linked above:

Quote

If you use the Timed Loop in an FPGA VI, you must use a single-cycle Timed Loop. A single-cycle Timed Loop executes one subdiagram per FPGA clock cycle. Single-cycle Timed Loops do not support frames.

This might be relevant too: https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z000000P8sWSAS&l=en-US

Edited September 28 by LogMAN

[ensegre]

AFAIR, from my very limited experience with a single model of FPGA, AI and AO conversions may take a long, variable number of clock cycles (dependent on routing perhaps, of the order of several tens of cycles), and therefore cannot sit in a SCTL. Don't take me literally though, I might be wrong and that may not be true for all FPGA boards.

[王佳]

1 hour ago, ensegre said:

据我所知，从我对单一型号 FPGA 的有限经验来看，AI 和 AO 转换可能需要很长时间，且时钟周期数不定（可能取决于路由，大约几十个周期），因此无法放在 SCTL 中。不过，不要从字面上理解我的话，我可能是错的，而且这可能不适用于所有 FPGA 板。

You're right. AI and AO cannot sit in a SCTL. And I don't need to have IO nodes in my loop. I now need a program to implement the equivalent of a timed loop instead of using SCTL directly. SCTL is too fast for me, I may only need 500k.The image I provided for example is an implementation of a timed loop, but it's not as efficient as I thought it would be. I would like to know if there is another way to write it.

Anyway, thanks for your reply!

[王佳]

23 hours ago, LogMAN said:

I'm not familiar with FPGAs so this might not work, but there is a Timed Loop in LabVIEW: https://www.ni.com/docs/en-US/bundle/labview-api-ref/page/structures/timed-loop.html

Edit: Just noticed this note in the article linked above:

This might be relevant too: https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z000000P8sWSAS&l=en-US

First of all, thank you for your response. I know about SCTL. But that's not what I need.🥰

[crossrulz]

You are limited by the max rate of the AI module. What module are you trying to read from?

[ensegre]

IIUC the OP, s/he put an AI node (which has a variable execution time) sequenced with a fixed delay inside a while loop, and then complains that the while loop is not repeating itself at 1/delay time. OTOH s/he says that s/he doesn't really need the AI. I'd answer here that, complexity permitting, since this is a deterministic target, the delay should be concurrent with the code executing in variable time, and that it should be longer than that execution time of the variable part. Then one iteration of the while loop would be guaranteed to take exactly as long as the delay.

Another option, if memory doesn't fail me, could be a SCTL tied to a secondary time reference, running at a submultiple of the master clock. If the complexity of the code doesn't allow execution within the prescribed timing, the compiler will then complain.

Can't say about the actual case, but often complex code can be simplified by factoring out, or by pipelining.

Edited September 29 by ensegre

[codcoder]

Can you put the AI node inside a single cycle timed loop with a slower clock?

On my FPGA target, 7820R, it is possible to create derived clocks with both lower and higher frequency compared to the base clock of 40 MHz.

Create a derived clock of 500 kHz -- if possible -- and connect that clock to the SCTL. If the compiler doesn't complain it maybe should work?

[王佳]

On 10/1/2024 at 2:05 PM, codcoder said:

Can you put the AI node inside a single cycle timed loop with a slower clock?

On my FPGA target, 7820R, it is possible to create derived clocks with both lower and higher frequency compared to the base clock of 40 MHz.

Create a derived clock of 500 kHz -- if possible -- and connect that clock to the SCTL. If the compiler doesn't complain it maybe should work?

My derived clock only goes as low as 4.69 MHz. My device is CRIO-9043

[Rolf Kalbermatter]

On 10/6/2024 at 8:33 AM, 王佳 said:

My derived clock only goes as low as 4.69 MHz. My device is CRIO-9043

That's normal for cRIOs. They don't usually go lower than a few MHz. I still use them whenever possible, except for loops that must contain nodes that can't be put into a single cycle loop at all. Quite often you do need pipelining anyhow at some point and then often need higher loop rates than your final desired rate and you can always implement your own internal counters that reduce the loop rate further and updates the outputs with the desired lower rate. 

[infinitenothing]

The analog input nodes won't be able to compile in a SCTL regardless of the rate you set. On the inside of the AI node, they need multiple cycles for the low level communication to the ADC chips. Like crossrulz says, the limiting factor is that chip. OP might be able to hit their target with an NI-9223. 

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019Km2SAE&l=en-US