cRIO Sine wave

[Iron_Scorpion]

See the attached screen shot. This crashes compilation.

 

"some of the compilation steps were not executed. refer to the Xilinx logâ€

The xilinx log is what looks like hundreds of pages. I see many warnings, but nothing that looks like a critical failure.

 

If I replace the sine wave with the square wave function, the code will run fine. 

 

I am running a cRIO-9067, with an NI-9269 module.

 

 

All I am looking for is a simple output sine wave VI. Freq and amp variable going in, and a waveform out of the RIO. 

Any help would be greatly appreciated. 

I have been using NI's examples (http://www.ni.com/white-paper/3780/en/#Example, fig2) linking to my hardware.

 

I suppose I'm looking for a few answers here:

1. Why does this fail compilation? 

2. Does anyone have a VI that will just simply output a sine wave?

 

Thanks again,

Chris

[Omar Mussa]

Are you compiling locally or using Cloud Compile?  I've had an issue where Cloud Compile threw an error and only (easiest?) way to fix was to compile locally - everything worked - after that point compiling in cloud was fine again.

[Iron_Scorpion]

Only Local

[MarkCG]

are you updated to the latest compactRIO support , 14.6? there are problems with that specific module and the 906x series chassis, though it may not be what you are seeing

 

http://digital.ni.com/public.nsf/allkb/EE21CD363EDE58E486257E0E0045C9A8

[JamesMc86]

The sine wave does use some different resources for the square wave (the cordic units on the FPGAs) but these should be available on all targets.

 

I would check that it is set to run outside a single cycle timed loop if that option is available in case this is impacting something.

[Iron_Scorpion]

Mark,

I am not using hybrid mode, so based on that link I didn't expect this to help.

I am running 2014 SP1 and rio 14.5, so I downloaded and installed rio14.6.

 

I rebuilt the above VI and it just compiled with no issues. That is awesome, thank you.

 

Unfortunately, the sine function is outputting a square wave (or a wave that looks more like a cap charge/discharge). My assumption right now is that this may be a casting issue with fixedpoint numbers. I'm digging into it.
 

[JKSH]

Hi,

 

Unfortunately, the sine function is outputting a square wave (or a wave that looks more like a cap charge/discharge).

 

1. What frequency is your output sine wave?
2. Do you get better results if you use lower frequencies?
3. How are you measuring the output?
    

    

   My assumption right now is that this may be a casting issue with fixedpoint numbers. I'm digging into it.

    

4. Do you get better results if you use RT code and the Scan Engine (instead of the FPGA) to output the waveform? (RT code can handle floating point numbers, so you're not restricted by fixed point)

[Iron_Scorpion]

1.       I have been trying frequencies all over the range. Ultimately I will need between 45hz, and 7.07kHz.

2.       No. I still get a sq wave.

3.       Fluke 175 RMS handheld meter, and a Tektronix TPS 2024B 200Mhz Oscope

4.       Scan mode is not apples to apples. In FPGA target I use the Sine Generator express VI, from the FPGA  pallet. That Vi is not an option from scan mode. As it stands right now, that VI is the problem. I can create a sine wave using the High throughput sine VI, in FPGA target mode. But it would be much easier to implement if the FPGA sine wave generator Express Vi would work. 

 

 

As a question on the side. Does anyone know the calculation for output frequency to phase increment (input my desired freq, get out the value that goes into the sine gen VI).  

In the sine generator example from LV, there is a PhaseIncrement.Vi. It has the equation as (Freq/FPGAClockRate)*(2**32).

Using this equation I can not get anywhere near a frequency I would expect. Should I not be using 40M for the FPGAClockRate?

[JKSH]

1.       I have been trying frequencies all over the range. Ultimately I will need between 45hz, and 7.07kHz.

2.       No. I still get a sq wave.

3.       Fluke 175 RMS handheld meter, and a Tektronix TPS 2024B 200Mhz Oscope

4.       Scan mode is not apples to apples. In FPGA target I use the Sine Generator express VI, from the FPGA  pallet. That Vi is not an option from scan mode. As it stands right now, that VI is the problem. I can create a sine wave using the High throughput sine VI, in FPGA target mode. But it would be much easier to implement if the FPGA sine wave generator Express Vi would work.

1. Ok, those are pretty low frequencies. There should be no problems there.
2. Strange...
3. Ok, the Tektronix is a good quality scope. There should be no problems there.
4. You're right, but it's much easier to get things working in Scan Mode. I suggested it as a preliminary test, to ensure that your hardware is working properly. (If you can't get it to work using RT code, then you won't get it to work using FPGA code)

 

 

As a question on the side. Does anyone know the calculation for output frequency to phase increment (input my desired freq, get out the value that goes into the sine gen VI).  

In the sine generator example from LV, there is a PhaseIncrement.Vi. It has the equation as (Freq/FPGAClockRate)*(2**32).

Using this equation I can not get anywhere near a frequency I would expect. Should I not be using 40M for the FPGAClockRate?

 

I haven't used these VIs myself, but the VI in your diagram looks different from the one in the NI example. Yours is http://zone.ni.com/reference/en-XX/help/371599K-01/lvfpga/sine_generator/ which doesn't seem to have a phase increment terminal.

 

Anyway, the formula at the NI example does not give you a frequency. It is a percentage, scaled to fit an unsigned 32-bit integer. (2³² = 100%, 0 = 0 %)

Edited June 15, 2015 by JKSH

[Iron_Scorpion]

Inside the express Vi properties for the sine, there is a check-box for additional inputs. The one input I'm using is Phase increment. An optional input is phase offset, I don't have that active since I don't need to phase shift.

what I expect the equation to do, is take my desired freq and calculate the necessary phase increment per clock tick for that freq.

Where does the 2^32 come from? Is this function forced to a 32bit integer?

 

I'm still wondering about the 40Mhz; is that the right clock freq to use? If my math is correct, dividing my frequency by 1.25Mhz for the clock should give me a phase increment very close to what I expect. I don't know why.

Is it that the FPGA clock is 40MHz, but a derived frequency is actually used for these calculations?

 

 

Again, thank you everyone for your continuous help.

[JKSH]

 

 

Inside the express Vi properties for the sine, there is a check-box for additional inputs. The one input I'm using is Phase increment. An optional input is phase offset, I don't have that active since I don't need to phase shift.

 

OK, the terminal was renamed from "Phase increment" to "Frequency (periods/tick)" LabVIEW 2014. I didn't realize this before, but they mean the same thing.

 

 

Where does the 2^32 come from? Is this function forced to a 32bit integer?

 

Look at Fig 2 in the example again carefully: The example VI takes an unsigned 32-bit integer in the "Phase increment" input. This datatype cannot represent fractions, so you multiply by 2³² to scale your input for maximum resolution.

 

However, your version (LabVIEW 2014) uses a fixed-point number, instead of an integer. This datatype can represent fractions, so you no longer need to multiply by 2³²

 

As I said before, your VI is not the same as what's shown in the example.

 

 

what I expect the equation to do, is take my desired freq and calculate the necessary phase increment per clock tick for that freq.

...

 

I'm still wondering about the 40Mhz; is that the right clock freq to use? If my math is correct, dividing my frequency by 1.25Mhz for the clock should give me a phase increment very close to what I expect. I don't know why.

Is it that the FPGA clock is 40MHz, but a derived frequency is actually used for these calculations?

 

The sine wave generator uses the top-level clock by default, which is 40 MHz. If you want, you can use a a derived clock by unchecking "Use top-level clock" and entering a custom clock frequency.

 

The "Frequency"/"Phase increment" input is the ratio of your sine wave frequency to the clock frequency used by this VI.

 

You don't divide by 1.25 MHz. Your top-level FPGA clock is 40 MHz, so:

• If you want a 400 kHz sine wave, Phase Increment = 400k/40M = 0.01 periods/tick
• If you want a 4 MHz sine wave, Phase Increment = 4M/40M = 0.1 periods/tick
• If you want a 40 MHz sine wave, Phase Increment = 40M/40M = 1 period/tick (this is not possible though)

 

Edited June 16, 2015 by JKSH