fpga For-loop in case structure on FPGA

[kull3rk3ks]

Hey,

 

I have an application where I need to sample at a specific higher rate to calculate RMS values and feed some of my values over FPGA front panel objects to a fast loop on my RT and send the samples at a slower rate (triggered by a timer) over a DMA FIFO to slower loop.

 

I Set the loop time to 10000 S/s and i'm filling up the DMA FIFO every 50 ms. The diagram looks something like this:

 

 

My question is: does the FPGA code execute the auto-indexed FOR-Loop like the Non-FPGA Diagram would, where the single Trigger bool from the timer remains true for all cycles of the for-loop, OR do I need to make sure the "Triggered" condition of the case structure is there for all FOR-Loop cycles? 

 

Thanks,

 

Robert

[Neil Pate]

The rules of data-flow are still valid, the value of the Triggered indicator is taken from the tunnel going into your for loop, so will have the same value for every iteration of the loop as it is really only "sampled" once on the very first iteration of the loop.

 

One thing to add, perhaps put in a control in the path of the Timed Out? feedback node to allow you to reset the timed-out latch, this can be useful during development.

[kull3rk3ks]

The rules of data-flow are still valid, the value of the Triggered indicator is taken from the tunnel going into your for loop, so will have the same value for every iteration of the loop as it is really only "sampled" once on the very first iteration of the loop.

 

One thing to add, perhaps put in a control in the path of the Timed Out? feedback node to allow you to reset the timed-out latch, this can be useful during development.

 

Thanks!

 Have a nice weekend.

[chris754]

I would also be careful with you local variable of "triggered" that is set to FALSE. There is no way, right now, that this is guaranteed to execute before or after the FOR loop, possibly causing unintended behavior. I would move it somewhere where you can guarantee the correct order of operation.

[Neil Pate]

I would also be careful with you local variable of "triggered" that is set to FALSE. There is no way, right now, that this is guaranteed to execute before or after the FOR loop, possibly causing unintended behavior. I would move it somewhere where you can guarantee the correct order of operation.

 

You are right, but this is probably less true on FPGA. As there is no data-flow dependency on this I would be very surprised if it did not reliably get cleared at the start of each iteration of the acquisition loop.

 

Defensive programming techniques are my preference so I would probably introduce some fake data-flow dependency to clear it at the start of each iteration.

[chris754]

I agree that in all likelihood that it would, but it could cause phantom bugs, that happen once-in-a-million times, and we all hate those.

[Neil Pate]

I agree that in all likelihood that it would, but it could cause phantom bugs, that happen once-in-a-million times, and we all hate those.

Million-to-one chances...crop up nine times out of ten

(especially on a Friday)

[chris754]

*always on a friday, right when you turn your laptop off.