Hey Dvido,
I would try verifying the FPGA code seperately. I think the issue probably lies in the host VI. The looping structure is doing a lot and running the FPGA code each time that I think may be causing undesired behaviour. Try a host first which is just a signal generator passing data into the FIFO and benchmark it to make sure its keeping up.
The other think to do is then benchmark the FPGA code. Put in some code to measure the loop rate and see what its achieving. If its too low then try benchmarking just the FIFO code and make sure it is reading fast enough, if not you could add another FIFO so you can perform some reads in parallel.
Finally if it is your host code that is the problem then try simplifiying it. Off the top of my head you can read only part of the TDMS file using the offset and length inputs on the top of the read so you don't have to load the whole file in. You could use single files again, open and close out of the loop and open a set length on each iteration. Then increment the offset with the iteration counter.
Will be interested to hear how it goes.
Regards,
Mac