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  1. I would like to design a FPGA module having an access to the resources like DIO,AIO or CAN which I can develop and test within one LabVIEW project and then use it within another. Idealy, I would like to have an API for RT implemented as a .lvlib and one VI which I have to drop on on my main FPGA vi. Currently, I have a .lvlib with virtual folders for RT and FPGA stuff. I have a few issues with this approach like requirement for changing FPGA typedef when I want to use it within another project and manual adding FIFO to the project. Well, I can live with this, but maybe you have a better approach which you woluld like to share. I have found something like FPGA Advanced Session Resources https://decibel.ni.com/content/docs/DOC-35574 , but still I am not sure whether it something I am looking for. Any thoughts?
  2. Hi all, I am trying to have an OOP based architecture inside RT ,where FPGA acquired values are used inside RT. So my plan is to have a generic base class upon which different systems(Child classes) are built. My child FPGA VIs will have additional controls in Front panel along with the common ones. So where can I put the FPGA ref? I cannot have it in base class since it will not bind all the controls. But if I have it in Child classes, how can I have the common functions in Base class? Looking forward to your suggestions guys..
  3. Question: How is 9*512 Discrete delays equal to ~410us? Context: We have found a solution to an offset problem between 2 sine waves, however we are unable to explain the delay calculations... (Someone else did the work a long time ago, now we need to explain the fix). There's 6us delay between the input Sinewave and the generated Sinewave from that input. Sinewave period is 416us (Figure 1). The Code works with 9 blocks of 512 Discrete Delays. 9*512*(1/80MHz) = 57.6us, but why is this working? Cannot Modify the code: The project is set and no code can be modified. Project Settings: The FPGA derived is at 80MHz, but the project Top-Level Clock seems to specify 40 MHz. The system automatically detects if there is an error greater than 5 degrees phase shift. Problematic: (http://prntscr.com/7ahhi5) Code: (http://prntscr.com/7ah2t3) Thanks
  4. Hi all, I am trying to compile an FPGA code which results in the error as follows: ERROR:HDLCompiler:1566 - "C:\NIFPGA\jobs\t1y1Y1O_hxEgG35\NiFpgaAG_0000002b_SequenceFrame.vhd" Line 42: Expression has 32 elements ; formal ceioparameter0signal expects 24 How do I debug this. I have no idea about how xilinx compilation. Help me Thanks, Prabhu
  5. Hello All, I have implemented first order filter in Real Time and trying to implement in FPGA. Please attached code for your reference.
  6. I am trying to drive a proportional solenoid valve: PVQ-33-5G-23-01N ( which responds to currents between 100mAand 165mA. I am using a circuit similar to the one in the attachment below except that I am using the myRIO's DAC in place of the AD5446, the LM324(http://www.ti.com/lit/ds/symlink/lm124-n.pdf) in place of the OP1177 and the MOSFET(http://www.mouser.com/Search/ProductDetail.aspx?R=VN3205N3-Gvirtualkey68900000virtualkey689-VN3205N3-G)[/url] So the challenge I am having is how to configure the circuit in labview. I am trying to use the default FPGA person ality of myRIO. I am supposed to generate a 1.2V Vref signal into the pin 3 of the LM324. By varying the word that is sent to the LM324, I am supposed to effectively vary the current on the Drain terminal of the mosfet. I have wired the Vref terminal to Connector C/AO0 on the myRIO and I have the VI below but I have no experience sending bits and bytes. I would love to drive the solenoid with about 10 -15 steps of current. Any help would be appreciated.
  7. Hello! Is there anything similar to "DMA MEMORY" that behaves like DMA FIFO, but without the FIFO part? I would like to transfer 1000 bytes of data from the FPGA to the cRIO host and 1000 bytes of data from the host to the FPGA and I don't care about old data - I only need the latest data. Ideally I would like to have two pieces of memory, each 1000 bytes long. One piece that can be written from the FPGA and read from the host and the other piece that can be written by the host and read by the FPGA, so that the first byte of data is always on the address 0. DMA FIFO is not a viable solution, because I would like to get the data as fast as possible, but I can read it on the host only on certain non deterministic intervals. If I would use the DMA FIFO, I would need a huge FIFO to store all the unused old measurements. Thank you for any reply or suggestion. Kind regards, Greg
  8. Hey, I have an application where I need to sample at a specific higher rate to calculate RMS values and feed some of my values over FPGA front panel objects to a fast loop on my RT and send the samples at a slower rate (triggered by a timer) over a DMA FIFO to slower loop. I Set the loop time to 10000 S/s and i'm filling up the DMA FIFO every 50 ms. The diagram looks something like this: My question is: does the FPGA code execute the auto-indexed FOR-Loop like the Non-FPGA Diagram would, where the single Trigger bool from the timer remains true for all cycles of the for-loop, OR do I need to make sure the "Triggered" condition of the case structure is there for all FOR-Loop cycles? Thanks, Robert
  9. Hey guys, I am currently having some issues with a FPGA program with Softmotion not compiling. We are running out of options in terms of how to get this FPGA program compiled. So my question is does compiling on Linux have a different probability of compiling FPGAs? I have heard that Xilinx Compiler is meant for Linux so it runs more efficiently and faster, so I was just wondering if the compile method was different as well
  10. Dear All, I have a question regarding to FPGA FIFO, specifically DMA from Host to Target (FPGA). As an Example, I have a 1D array containing 10x2000 elements stored inside the host side Buffer. At the FPGA side, I want to use 'host to target-read' to read fixed amount of elements from the host side buffer, for example exact 2000 elements. Moreover I want to hold onto the data (2000 elements) for a certain amount of time (example 10s) before reading again 2000 elements from the buffer. Does anyone have a clue how to do this? Thank you so much! Yang
  11. FPGA Scripting is now generally available. FPGAScripting.zip
  12. Hi , I am a power systems engineer and I am new to Labview and Labview FPGA. The hardware that I am using is an sbrio 9642. I am using Labview 2013. The following is my application I have a three phase measurement of a substation. The three phase voltages are stepped down to +/- 2.7 v (270 volts actual). I am using the built in analog inputs to take these voltages. I have six inputs, two three phase voltages line to neutral. I want to measure the three phase frequency of these signals (Two frequency measurements in total). I want to use the built in three phase pll in the FPGA math and analysis palette. It is ideally built for such application. But, for some reason I am not able to get the right frequency (Which should be 60 HZ). I have also opened a discussion in the "Power electronics development community". I have all my files in this community. I recently found about "LAVA". So, I am posting this discussion again to get some help. I specifically want to use this method because in this way all the calculation will be done in the FPGA level and I can have the real time processor in the SBRIO for communication pruposes. For more information about this please check this link https://decibel.ni.com/content/message/63258#63258 Frequency_calculation.zip
  13. I'm working with a contractor on a cRIO-based test system, and we are arranging a shared version control scheme so I can work on the code as well. One issue is that there are 2 different cRIO systems operating in completely different network environments, and there are currently 3 different locations where we have to change the IP address between environments: 1. RT controller properties in project 2. A front-panel control on a UI vi that connects to the RT controller 3. A constant in an RT Main vi to set the target for the FPGA BitFile I'd prefer to make this more portable and more easily maintainable in this shared satting under VCS, ideally just popping up a panel that offers controllers to connect to so the operator just clicks on a system to connect to. Desired features would be: 1. Dynamically identifies connected cRIO controllers 2. Offers choice of controller to connect with 3. Remembers last choice with ini file and automatically connects if there is only 1 possible target Thank you for any help. Ryan Rutledge
  14. Hi everyone, I will be presenting TS1360: "Implementing an Efficient Moving Average Filter in LabVIEW FPGA" on Thursday 1-2pm. Room 16B. These techniques are relevant for developing any sort of code on the FPGA, not necessarily filters. Many of the findings are a bit counter-intuitive for someone used to developing regular LabVIEW code or even Real-Time LabVIEW code. Hope to see some of you there or bump into you in the corridors of the Convention Centre! Cheers, Neville.
  15. Hi, I am doing a project which required high speed data commnication between 2 chassis. 24 Double digital numbers in a loop rate 10K. The first thing come to my mind is using reflective memory. But the result is not good enough. The data transfer tooks 80% of time in the 10K loop, Then to avoid loop late, I could not do any thing else in this loop. Is there any option else? Maybe using digital I/O in FPGA card? Thanks in advance!
  16. CAR# 378165 LabVIEW Version 11.0.1f2 In a VI for a FPGA target, if an error cluster is wired to one input of an OR gate that has a Boolean wired to the other input, then in the "generate intermediate files" process that precedes the Xilinx bitfile generation, "stage 1 of 7" (analyzing VI hierarchy) will very repeatably crash while processing the VI. See attached PDF.
  17. Hello there! I'm currently working on the control of a machine that does a specific measurement while the sensor (composed of several strain gauges) slides along a sled. I would like to acquire the sensor Data and to relate it to the position of the sled. The machine also has simple User inputs as Buttons and simple outputs as LEDs. The motors are controlled by relais which are connected to DOs. I wanted to use the cRIO Wfm reference library for my project because it seems to be great at this task. My current problem is that whenever I try to start a measurement, I get the error message CompactRIO: (Hex 0xFE4C) You have entered a data rate that is not supported by the selected module and oversample clock frequency. As a matter of fact though, I know that the Delta sigma strain gauge modules support a sampling rate of 10.000S/s but I seem to get the error from the FPGA. I'll attach my FPGA VI and the Measure VI (which is normally located inside a statemachine) for your reference. - all of them written in LV2012. I also get the same error when Using the example VI provided in the RIO Wfm Library. Thank you for reading and eventually helping Untitled 1.vi Measurement.vi FPGA-Main.vi
  18. Hello, everyone! I wanted to introduce the new MH-LCD-216, the very first cRIO display module. This is something that we know a lot of people have been asking for, so we are very excited to offer this new module to the LabVIEW community. We debuted the MH-LCD-216 at NI Week 2012 and the positive feedback was overwhelming. The website below has additional information and don't hesitate to give me a call or post here with any questions. MH-LCD-216 cRIO Display Module Happy compiling! Jpeg
  19. Here is an interesting topic about adding C-series discovering capabilities to RMC custom boards for SbRIO : http://forums.ni.com/t5/cRIO-Module-Developers-Kit/Can-C-series-module-MDK-can-be-applied-to-SbRIO-mezzanine-card/td-p/1921829 Do not hesitate to post comments on the NI thread or through this forum.
  20. I'm attempting to compile an FPGA project for an R series card to use in Veristand 2011. I used the FPGA creator wizard to get the basic template and modify my IO as directed. When I attempt to build the project, I get the following error. 'LabVIEW: Generic file I/O error.' ========================= NI-488: I/O operation aborted. Error 6 occurred at Write to Text File in niFpgaCompileWorker_SaveStatus.vi-> niFpgaCompileWorker_Status_Publish.vi-> niFpgaCompileWorker_GetStatus.vi->niFpgaCompile_Worker.vi:1 Possible reason(s): LabVIEW: Generic file I/O error. ========================= NI-488: I/O operation aborted. C:\NIFPGA\compilation\TheFPGA_FPGATarget_TheFPGA_0E9FD350\BuildResults.lvtxt My first thought was that the file size was too long. (I had the project buried in a deep heirarchy with a long job number in the name.) I reduced the size of the FPGA project, target, and folder name then moved the project to C:\ . The name shouldn't be an issue now. Any ideas? The error is so generic that it doesn't feel very helpful.
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