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  1. Hello All, I have implemented first order filter in Real Time and trying to implement in FPGA. Please attached code for your reference.
  2. I am trying to drive a proportional solenoid valve: PVQ-33-5G-23-01N ( which responds to currents between 100mAand 165mA. I am using a circuit similar to the one in the attachment below except that I am using the myRIO's DAC in place of the AD5446, the LM324(http://www.ti.com/lit/ds/symlink/lm124-n.pdf) in place of the OP1177 and the MOSFET(http://www.mouser.com/Search/ProductDetail.aspx?R=VN3205N3-Gvirtualkey68900000virtualkey689-VN3205N3-G)[/url] So the challenge I am having is how to configure the circuit in labview. I am trying to use the default FPGA person ality of myRIO. I am suppose
  3. Hello! Is there anything similar to "DMA MEMORY" that behaves like DMA FIFO, but without the FIFO part? I would like to transfer 1000 bytes of data from the FPGA to the cRIO host and 1000 bytes of data from the host to the FPGA and I don't care about old data - I only need the latest data. Ideally I would like to have two pieces of memory, each 1000 bytes long. One piece that can be written from the FPGA and read from the host and the other piece that can be written by the host and read by the FPGA, so that the first byte of data is always on the address 0. DMA FIFO is not a viable
  4. Hey, I have an application where I need to sample at a specific higher rate to calculate RMS values and feed some of my values over FPGA front panel objects to a fast loop on my RT and send the samples at a slower rate (triggered by a timer) over a DMA FIFO to slower loop. I Set the loop time to 10000 S/s and i'm filling up the DMA FIFO every 50 ms. The diagram looks something like this: My question is: does the FPGA code execute the auto-indexed FOR-Loop like the Non-FPGA Diagram would, where the single Trigger bool from the timer remains true for all cycles of the for-loop,
  5. Hey guys, I am currently having some issues with a FPGA program with Softmotion not compiling. We are running out of options in terms of how to get this FPGA program compiled. So my question is does compiling on Linux have a different probability of compiling FPGAs? I have heard that Xilinx Compiler is meant for Linux so it runs more efficiently and faster, so I was just wondering if the compile method was different as well
  6. Dear All, I have a question regarding to FPGA FIFO, specifically DMA from Host to Target (FPGA). As an Example, I have a 1D array containing 10x2000 elements stored inside the host side Buffer. At the FPGA side, I want to use 'host to target-read' to read fixed amount of elements from the host side buffer, for example exact 2000 elements. Moreover I want to hold onto the data (2000 elements) for a certain amount of time (example 10s) before reading again 2000 elements from the buffer. Does anyone have a clue how to do this? Thank you so much! Yang
  7. FPGA Scripting is now generally available. FPGAScripting.zip
  8. Hi , I am a power systems engineer and I am new to Labview and Labview FPGA. The hardware that I am using is an sbrio 9642. I am using Labview 2013. The following is my application I have a three phase measurement of a substation. The three phase voltages are stepped down to +/- 2.7 v (270 volts actual). I am using the built in analog inputs to take these voltages. I have six inputs, two three phase voltages line to neutral. I want to measure the three phase frequency of these signals (Two frequency measurements in total). I want to use the built in three phase pll in the FPGA ma
  9. I'm working with a contractor on a cRIO-based test system, and we are arranging a shared version control scheme so I can work on the code as well. One issue is that there are 2 different cRIO systems operating in completely different network environments, and there are currently 3 different locations where we have to change the IP address between environments: 1. RT controller properties in project 2. A front-panel control on a UI vi that connects to the RT controller 3. A constant in an RT Main vi to set the target for the FPGA BitFile I'd prefer to make this more portable and more eas
  10. Hi everyone, I will be presenting TS1360: "Implementing an Efficient Moving Average Filter in LabVIEW FPGA" on Thursday 1-2pm. Room 16B. These techniques are relevant for developing any sort of code on the FPGA, not necessarily filters. Many of the findings are a bit counter-intuitive for someone used to developing regular LabVIEW code or even Real-Time LabVIEW code. Hope to see some of you there or bump into you in the corridors of the Convention Centre! Cheers, Neville.
  11. Hi, I am doing a project which required high speed data commnication between 2 chassis. 24 Double digital numbers in a loop rate 10K. The first thing come to my mind is using reflective memory. But the result is not good enough. The data transfer tooks 80% of time in the 10K loop, Then to avoid loop late, I could not do any thing else in this loop. Is there any option else? Maybe using digital I/O in FPGA card? Thanks in advance!
  12. CAR# 378165 LabVIEW Version 11.0.1f2 In a VI for a FPGA target, if an error cluster is wired to one input of an OR gate that has a Boolean wired to the other input, then in the "generate intermediate files" process that precedes the Xilinx bitfile generation, "stage 1 of 7" (analyzing VI hierarchy) will very repeatably crash while processing the VI. See attached PDF.
  13. Hello there! I'm currently working on the control of a machine that does a specific measurement while the sensor (composed of several strain gauges) slides along a sled. I would like to acquire the sensor Data and to relate it to the position of the sled. The machine also has simple User inputs as Buttons and simple outputs as LEDs. The motors are controlled by relais which are connected to DOs. I wanted to use the cRIO Wfm reference library for my project because it seems to be great at this task. My current problem is that whenever I try to start a measurement, I get the erro
  14. Hello, everyone! I wanted to introduce the new MH-LCD-216, the very first cRIO display module. This is something that we know a lot of people have been asking for, so we are very excited to offer this new module to the LabVIEW community. We debuted the MH-LCD-216 at NI Week 2012 and the positive feedback was overwhelming. The website below has additional information and don't hesitate to give me a call or post here with any questions. MH-LCD-216 cRIO Display Module Happy compiling! Jpeg
  15. Here is an interesting topic about adding C-series discovering capabilities to RMC custom boards for SbRIO : http://forums.ni.com/t5/cRIO-Module-Developers-Kit/Can-C-series-module-MDK-can-be-applied-to-SbRIO-mezzanine-card/td-p/1921829 Do not hesitate to post comments on the NI thread or through this forum.
  16. I'm attempting to compile an FPGA project for an R series card to use in Veristand 2011. I used the FPGA creator wizard to get the basic template and modify my IO as directed. When I attempt to build the project, I get the following error. 'LabVIEW: Generic file I/O error.' ========================= NI-488: I/O operation aborted. Error 6 occurred at Write to Text File in niFpgaCompileWorker_SaveStatus.vi-> niFpgaCompileWorker_Status_Publish.vi-> niFpgaCompileWorker_GetStatus.vi->niFpgaCompile_Worker.vi:1 Possible reason(s): LabVIEW: Generic file I/O error. ===============
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