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In FPGA VI an error cluster connection to a Boolean input causes crash


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CAR# 378165

LabVIEW Version 11.0.1f2

In a VI for a FPGA target, if an error cluster is wired to one input of an OR gate that has a Boolean wired to the other input, then in the "generate intermediate files" process that precedes the Xilinx bitfile generation, "stage 1 of 7" (analyzing VI hierarchy) will very repeatably crash while processing the VI. See attached PDF.

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