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Reading fixed size of elements using FPGA FIFO


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Dear All,

 

I have a question regarding to FPGA FIFO, specifically DMA from Host to Target (FPGA).

 

As an Example, I have a 1D array containing 10x2000 elements stored inside the host side Buffer.

 

At the FPGA side, I want to use 'host to target-read' to read fixed amount of elements from the host side buffer, for example exact 2000 elements. Moreover I want to hold onto the data (2000 elements) for a certain amount of time (example 10s) before reading again 2000 elements from the buffer.

 

Does anyone have a clue how to do this?

 

Thank you so much!

 

Yang

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What do you want to do with those 2000 elements during the 10s? Storing a 2000-element array on the FPGA in logic may not be a good use of space. Also, you can only ever read one element at a time from the DMA FIFO on the FPGA, so you'll need a loop that iterates 2000 times to read all 2000 elements. Depending on what you want to do with that data, you may want to read from the DMA FIFO into a memory block, then read values out of the memory block in a separate loop.

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Just to add to Jordan's post for those that don't know.

 

His picture shows an efficient way of reading from the DMA FIFO, first check to see if there are enough elements by requesting zero with a zero timeout, this will return the number elements remaining. Then only perform the actual read if the number of available elements is equal to (or more than) what you want.

 

My understanding of this necessity is that although the transfer occurs via DMA, if there are not enough elements yet then the CPU actually polls (using a lot of resource) until the number of elements is achieved, and this can really kill performance.

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My understanding of this necessity is that although the transfer occurs via DMA, if there are not enough elements yet then the CPU actually polls (using a lot of resource) until the number of elements is achieved, and this can really kill performance.

You can request 0 elements from the DMA to obtain the number of elements waiting.

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Just to add to Jordan's post for those that don't know.

 

His picture shows an efficient way of reading from the DMA FIFO, first check to see if there are enough elements by requesting zero with a zero timeout, this will return the number elements remaining. Then only perform the actual read if the number of available elements is equal to (or more than) what you want.

 

My understanding of this necessity is that although the transfer occurs via DMA, if there are not enough elements yet then the CPU actually polls (using a lot of resource) until the number of elements is achieved, and this can really kill performance.

 

A picture says a thousand words :P , but yes I included both parts to demonstrate a good way to check if the elements exist before attempting to read them.  Regarding your last point, I would suggest at least employing a timeout if someone isn't going to do the initial check.  The host loop should be structured in such that it doesn't need data every iteration (if you are looking for a chunk of buffered data), or manually provide your own polling by placing something like what I have in the picture in a loop with a timing element. 

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A picture says a thousand words :P , but yes I included both parts to demonstrate a good way to check if the elements exist before attempting to read them.  Regarding your last point, I would suggest at least employing a timeout if someone isn't going to do the initial check.  The host loop should be structured in such that it doesn't need data every iteration (if you are looking for a chunk of buffered data), or manually provide your own polling by placing something like what I have in the picture in a loop with a timing element. 

 

The point I was trying to get across (unsuccessfully it seems!) is that even with a timeout a lot of CPU is used up waiting for the DMA buffer to have enough elements. This is probably contrary to what most people would expect.

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The point I was trying to get across (unsuccessfully it seems!) is that even with a timeout a lot of CPU is used up waiting for the DMA buffer to have enough elements. This is probably contrary to what most people would expect.

I understood, but yes some might not.  The point I was trying to get across is that in that situation a timeout is better than nothing, i.e. waiting/polling the entire time for the number of elements to become available.  Either way, the picture is the better approach and allows the loop to do other things.

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This is all fine and good, but the poster specifically said that they're using a "Host-to-Target" DMA FIFO, which means the DMA FIFO Read is on the FPGA side, where it is only possible to read a single element at a time, so yes, a loop is required.

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This is all fine and good, but the poster specifically said that they're using a "Host-to-Target" DMA FIFO, which means the DMA FIFO Read is on the FPGA side, where it is only possible to read a single element at a time, so yes, a loop is required.

:oops:

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