Jump to content

How to Implement first order filter in FPGA


pravin

Recommended Posts

Hi,

 

Have a look at the FPGA Math & Analysis VIs and Functions. There are ready-made Butterworth and Notch filters.

 

By the way, if you want to post any code in the future, open your LabVIEW Block Diagram, select the code, and click "Edit" -> "Create VI Snippet from Selection". That produces a high-quality PNG file that other users can import directly into LabVIEW to test your code.

  • Like 1
Link to post

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Similar Content

    • By Ricardo de Abreu
      Hi guys. This semester I'm starting a course system development for control and automation engineering, witch will be based on LabView. Therefore, my University doesn't have a NI hardware, even a MyRIO for us to test our VI and the teacher said that we should test our projects with our own Arduino...
      So, I have a little experience in Arduino and I know the basics for LabView. Now I'm in a point that I know that with Arduino I'll not take the best from LabView. I cannot even deploy a code to it.
      So, there is where my question comes in...
      I'm looking for a new board better then Arduino to use in the classes. I would buy a MyRIO card if I had the money but in Brazil this board is too expensive for me
       Witch one should I get that is closest to myRIO and less expensive than that? I would like to try de deployment of a VI and FPGA..... Is this possible?
      Thanks a lot for the help!
      Regards
    • By Moes
      Hello everyone i am relative new to labview and currently i am bit stuck need help...
      i want to capture data with a digital trigger on my chassis PFI0 (9178), the pulse is 20ms long and occurs on my straingauge 9237 module.
      The pulse comes in 10 times in a row with couple of miliseconds between it, can i measure it every time and push it inside an array like a "last in first out" memmory to evaluate it slower for the user?
       
      I am currently struggeling with the loop dividing into more then one loop approach.
       
       
      How to breach out from accquire->store->plot in one loopdone right with good performance? I don't know how to shape the cure because there is a dependency from loop time to datapoints with the daqmx task inside of it :-/
      Capturing should always be possible and run in background and the user just uses the frontend to play around with filters (me learning what filter shape the cure in which way)
       
      It would be nice if someone can share their knowledge towards realizing multiple graphs from a pulse that comes in and is stored in a graph.
      I know my program is not pretty right now but with progress it will be nicer, function first to learn!

      WheatstoneSix_6.vi
    • By grjgrj
      Hello. I need change some code for SbRIO-9626 with LabVIEW 2018. I have code from LabVIEW 2015. Right now I have only LabVIEW 2018. And I worked with it for SbRIO-9627.
      LabVIEW FPGA, LabVIEW Real-Time, NICRIO1800 driver istalled.
      And I install Xilinx ISE 11.5 Compilation Tool too. 
      When I start compilation FPGA VI I got error about problem with compilation too (see attachment picture).
      Could you tell me how I can solve this problem? 
      It is very important. 

    • By thoraz
      I have created a sub-vi which un-pack data comnig from an embedded board with 8 channels and puts on its output the results. Now I'd like to implement an addictional feature which regards the filtering of this data through a low and high pass. So I created another sub-vi that integrate these kind of filters with inputs to set their configuration.
      When I use the filtering sub-vi on only one channel all seems to work well, but as soon as I add another one on another channel it doesn't work: the output signals are not filtered; there some changes in their trends but it's a indefinite behavior, not a low/high pass processing. It seems thet the presence of one filtering sub-vi intereferes with the other. I tryed to understand the problem but actually I'm in a dead end.
      Can anyone give me any suggestion or maybe a solution?
      filtering.vi
      unpack.vi
    • By prabhakaran
      Hi,
       
       
      I am trying to use image convolution inside FPGA. My Image size is around 6kx2k. The convolution is applied properly until 2600 pixels in x resolution. After that, the values seem to miss previous row data. 
       
      In Detail: As convolution is matrix operation, image data needs to be stored for the operation. But it seems there is an inadvertent error storing only 2600 pixels per row inside FPGA. And hence the filtered output is calculated assuming these pixels to be 0. 
       
      I have tried with different image sizes, different convolution kernels, and also in different targets (cRIO 9030 and IC 3173). All results are same.
       
      I have attached a screenshot of FPGA VI and an example image.
       
      The example image shows an input image of 4000x2500 of same pixel value 16.The kernel is 3x3 of values 1 with divider=1. The RT image is processed using IMAQ convolute inside RT controller and has value 144 [(9*16)/1] for all pixels. But the FPGA processed image (zoomed in) has 144 until 2597 pixels and then 112 (7*16- showing 1 column of 2 rows missing) at 2598, 80 (5*16- showing 2 columns of 2 rows missing) at 2599 and 48 after that (missing 3 columns of 2 rows- current row is always present). This shows the data is missing from the previous rows after 2600 index.
       
      Is there some mistake in the code or any workaround available?


×
×
  • Create New...

Important Information

By using this site, you agree to our Terms of Use.