Jump to content

Accessing FPGA Indicator Latency (cRIO)


Yohann

Recommended Posts

Hello,

I'm currently encountering a problem when accessing FPGA indicator with "Reading/ writing a control" node

The FPGA part acquires data every 10µs

The RT part Read the indicator every 2000µs

But when Running the VIs, I see that the elapsed time between 2 Readings of the indicator change from one iteration to another

Can someone help me?FPGA.pngRT.png

Link to comment

What sort of jitter are you seeing? What were you expecting? How much can you tolerate?

If you have to have better jitter try:

  1. Move the indicators outside the loop. When you write to an indicator in development mode, it needs to use the network. You might also want to move the controls outside too and use something like a single process single element RT FIFO shared variable
  2. Turn off debug
  3. Replace the while loop with a timed loop
Link to comment

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Guest
Unfortunately, your content contains terms that we do not allow. Please edit your content to remove the highlighted words below.
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

×
×
  • Create New...

Important Information

By using this site, you agree to our Terms of Use.