I'm a beginner in labview, and now test cRIO about two weeks. I still can not solve the problem. I attach my test project for explanation.
I want to realize that , for example, with time sequence t1, t2, t3, t4, DO outputs T, F, T, F, AO1 outputs A1, A2, A3, A4, AO2 outputs B1, B2, B3, B4, and the delay of AO1 and AO2 should as small as possible(AO1 and AO2 may comes from difference modules).
I search in Google, NI forum, and decide to use for loop and loop timer in FPGA.
The reason as follow:
1. To realize the specific time interval, I can use Wait and Loop timer. But in "FPGA 0--Test DO.vi", it can't not realize specific time interval by several us's error(maybe large). And to complete once of while loop, it needs 134us. I can't explain that it can realize time interval below 134us, even I acturally realize a delay of 10us, but the input is not acturally 10us, so it's not accurate.
And by NI example, I use the Loop timer.
2. In "FPGA 1--Test DO and AO.vi", I find that the loop timer helps me to realize accurate time interval, however, it ignore the first time interval. Such as, t1, t2, t3, t4, with disired output A1, A2, A3, A4. It goes A1(t2), A2(t3), A3(t4), A4(t1). And in "FPGA 2--Test DO and AO.vi", it has same problem. DO0 and AO1 goes A1(t2), A2(t3), A3(t4), A4(t1). And AO0 is always ahead of DO of t1.
The people of NI forum advice that I should put AO0 and AO1 into one FPGA/IO node and use SCTL. But up to now, I don't find any example about it(Google or NI forum, maybe it's primary). Mainly that AO0 and AO1 must go with different timeline, the dimension of input array is different. Can anyone offer advice for me?
By Ricardo de Abreu
Hi guys. This semester I'm starting a course system development for control and automation engineering, witch will be based on LabView. Therefore, my University doesn't have a NI hardware, even a MyRIO for us to test our VI and the teacher said that we should test our projects with our own Arduino...
So, I have a little experience in Arduino and I know the basics for LabView. Now I'm in a point that I know that with Arduino I'll not take the best from LabView. I cannot even deploy a code to it.
So, there is where my question comes in...
I'm looking for a new board better then Arduino to use in the classes. I would buy a MyRIO card if I had the money but in Brazil this board is too expensive for me
Witch one should I get that is closest to myRIO and less expensive than that? I would like to try de deployment of a VI and FPGA..... Is this possible?
Thanks a lot for the help!
Hello. I need change some code for SbRIO-9626 with LabVIEW 2018. I have code from LabVIEW 2015. Right now I have only LabVIEW 2018. And I worked with it for SbRIO-9627.
LabVIEW FPGA, LabVIEW Real-Time, NICRIO1800 driver istalled.
And I install Xilinx ISE 11.5 Compilation Tool too.
When I start compilation FPGA VI I got error about problem with compilation too (see attachment picture).
Could you tell me how I can solve this problem?
It is very important.
I am trying to use image convolution inside FPGA. My Image size is around 6kx2k. The convolution is applied properly until 2600 pixels in x resolution. After that, the values seem to miss previous row data.
In Detail: As convolution is matrix operation, image data needs to be stored for the operation. But it seems there is an inadvertent error storing only 2600 pixels per row inside FPGA. And hence the filtered output is calculated assuming these pixels to be 0.
I have tried with different image sizes, different convolution kernels, and also in different targets (cRIO 9030 and IC 3173). All results are same.
I have attached a screenshot of FPGA VI and an example image.
The example image shows an input image of 4000x2500 of same pixel value 16.The kernel is 3x3 of values 1 with divider=1. The RT image is processed using IMAQ convolute inside RT controller and has value 144 [(9*16)/1] for all pixels. But the FPGA processed image (zoomed in) has 144 until 2597 pixels and then 112 (7*16- showing 1 column of 2 rows missing) at 2598, 80 (5*16- showing 2 columns of 2 rows missing) at 2599 and 48 after that (missing 3 columns of 2 rows- current row is always present). This shows the data is missing from the previous rows after 2600 index.
Is there some mistake in the code or any workaround available?
I'm about to write an application that can create a complete new FPGA-Project for the cRIO-system automatically without any user Input.
Before I ask my question directly, I will give you a few Information about the system and how it works at the moment.
I'm working with a cRIO-system that can have different modules in different slots (max 8). That system should be universally usable which means I can replace one module with another one at the start up and create a complete new project with a different name.
Most of the project works (I can find out in which slots which module is placed and load the right VI's correctly) but there is one point which I really dislike: the user always has to give some input Information at the beginning of the creation and mostly that is the same like "Which type of project it should be" or "Which IP address should be used to find the system and the modules for each slot".
The goal is that I can write down some specific arguments so the program is created automatically?
Or - if there is no way to do this - a way that a second window is shown on screen to help the user through the creation process (for example that tells the user that the system need to be turned on that the project can find every single module)?
English isn't my mother tongue, so please apologize if there are any mistakes in my spelling.
Thank you very much for your help