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Jordan Kuehn

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Everything posted by Jordan Kuehn

  1. Ah yes, you are reminding me of some specifics regarding the modules accepting integers when used in the FPGA and if the calibration mode is set to "Raw". Here are some notes I have from working with a 9263 (quite some time ago) which should be similar. Note explicitly casting types in the host sine wave properties VI (first picture) that produces the properties for signal generation that are passed to the FPGA code (second picture). The FXP constants wired in to the casting configures the bit word lengths. https://www.ni.com/documentation/en/labview-comms/latest/data-types/intro-fixed-point-numbers/ Perhaps you have adequately addressed this, but I've been burned on this in the past. Anyway, some of these examples might help illustrate the signal generation being done in the FPGA itself if that helps.
  2. Is your amplitude correct? It looks like you are trying to command nearly +/-2000V output. Also you have a lot of coercion dots with your fixed points. Try to get those to be consistent. It's not as important with floats and integers, but you can get some strange stuff going on depending on how the bits are allocated going from FXP to FXP.
  3. I've done some of this in the past (when SCC decided to "merge" my lvproj file), and it seemed straightforward enough. I think I recall the primary reason it is unsupported is because they can change the xml structure at will. Currently I have use for this because I have one cRIO on my desk to test with and another in a system to deploy to. If only we had a way to virtualize targets, but that's a different can of worms!
  4. I'm not surprised by this, but thank you for weighing in. Maybe when NXG reaches CG parity in 2050.
  5. Thank you for the confirmation. I have done something similar using numeric types, but it is inconvenient at best. An NXG version of this toolkit would be fantastic.
  6. I've been using this toolkit when passing data to a WebVI in LabVIEW NXG 5.0.0. It appears that the JSON parser built into NXG WebVIs is incapable of reading enums or timestamps. I am not certain if that is a limitation of the parser or the encoder. Are you able to shed any light on this drjdpowell?
  7. I have tried and experienced similar results. I have been able to accomplish simple tasks by calling python from the System Exec.vi with the appropriate parameters and such. It's slow, but is ok for some things. It did require using the Chroot/SSH "Trick".
  8. @Steve Drouilhet No problem. I believe it was this toolkit: https://github.com/Indie-Energy/AWS-IoT-RESTful and the license is pretty wide open I believe. If I have a chance I'll see if I can pack it up and contribute to the project on the github. I'm also using the WireFlow toolkit (paid) for some MQTT projects with a broker that I've set up. I was initially drawn to the Indie-Energy one even though I have a WF toolkit license since it was more plug and play for AWS. I do think now after learning more about the AWS IoT stuff that either will work, but also that I don't want to work with AWS IoT if I can help it. Note, the WF toolkit does not use the native LV2020 implementation and they do not have plans to do so. The reason I replaced the IE toolkit TLS code is because I had issues on Linux RT and that fixed it. I have not had issues in general with WF on RT, but I'm not using TLS in that application (yet).
  9. I have not used this particular client, but have done something similar with AWS and MQTT and a different client. I wound up stripping out all the OpenSSL stuff for the new native LabVIEW tools. Here is what worked for me during some initial tests. It may not be perfect, but hopefully it's a start at least. After that it's regular TCP Read/Write.
  10. Thanks, that is almost exactly what I've taken to doing.
  11. I just found this thread and have been getting hit by this pretty hard on my current project. That and classes locking when I have a typedef used on two targets. LV 2020. Is the answer really just to break my projects apart into Windows and RT? I've not had to do this in the past, but I haven't had as extensive use of classes on the RT side before.
  12. You might check the folder permissions for the folder you created. I have ran into issues with that before.
  13. I've used this in the past as an inexpensive insurance policy. I've never had to restore from backup though. https://www.backblaze.com/cloud-backup.html
  14. I get that one some projects and not others. I'm used to being able to close out the project and it closing everything else out and prompting to save. But I don't think that's only on 2020, I have it in 2018 as well, same projects.
  15. Thanks for all the links. I had seen discussion some time back and had never jumped through the hoops to make it happen. Currently I have three different cRIOs on my desk which gets to be expensive. I'll give this a shot!
  16. I was getting this in LV2018. I get something similar still in LV2020, as well as projects that don't seem to leave memory even after they are all closed out to the main LV screen. They open back up instantly.
  17. I'll be honest, the very basic Event Logger Library from NI meets my needs 95% of the time. I have heard of an offering from DMC called Llama while attending one of the local user groups in Chicago, but haven't had any time to give it a shot.
  18. It seems to me that it sometimes wants to open the VIPM Browser instead or if one is open the other one doesn't want to open. I need to retrace my steps to recreate the issue, but I noticed some strange behavior in the past, also in a VM. A restart got things working again too.
  19. Thank you for the pointers. Unfortunately that didn't work either. Does the ioctrl c command behave differently than spidev in python? I may be able to give this a shot again in some time, but for now I was able to use a combination of the SSH trick and calling python commands from the CLI to get things working, albeit slowly. Figured I would at least leave a note here for now.
  20. At risk of derailing my own topic I'd like to see if someone might be able to shed some light on my original problem. Below is a snippet of code that I've put together in an attempt to replicate a python routine that is not functioning properly. It works fine in python. Address is 1 and I have tried a variety of CS pins, modes, bit order, and asserting the Frame line or not. And the Python routine attached, relevant sections below. This is for a RELAYPlate hat. GPIO.setmode(GPIO.BCM) RELAYbaseADDR=24 ppFRAME = 25 ppINT = 22 GPIO.setup(ppFRAME,GPIO.OUT) GPIO.output(ppFRAME,False) #Initialize FRAME signal time.sleep(.001) #let Pi-Plate reset SPI engine if necessary GPIO.setup(ppINT, GPIO.IN, pull_up_down=GPIO.PUD_UP) spi = spidev.SpiDev() spi.open(0,1) localPath=site.getsitepackages()[0] helpPath=localPath+'/piplates/RELAYhelp.txt' #helpPath='RELAYhelp.txt' #for development only RPversion=1.1 # Version 1.0 - initial release # Version 1.1 - adjusted timing on command functions to compensate for RPi SPI changes def getID(addr): global RELAYbaseADDR VerifyADDR(addr) addr=addr+RELAYbaseADDR id="" arg = list(range(4)) resp = [] arg[0]=addr; arg[1]=0x1; arg[2]=0; arg[3]=0; ppFRAME = 25 GPIO.output(ppFRAME,True) null=spi.xfer(arg,300000,60) #null = spi.writebytes(arg) count=0 # time.sleep(.01) while (count<20): dummy=spi.xfer([00],500000,20) if (dummy[0] != 0): num = dummy[0] id = id + chr(num) count = count + 1 else: count=20 GPIO.output(ppFRAME,False) return id RELAYplate.py
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