Jump to content

Running out of LUTs on Zynq 7020

Go to solution Solved by shoneill,

Recommended Posts

Hi FPGA expert.

When I try “my way†of implementing a simple FPGA Analog Out VI, I run out of FPGA fabric (too may LUTs used).

So what better way can I do this (if there is one), that don’t overuse my LUTs.

My task is to:

Make one analog measurement and control 2 analogue outputs that should be clocked out every time I get a digital trigger in.


I’m running a sbRIO-9637 (Zynq7020)

I’ve attached the simple application and I’m puzzled of what needs so many Look Up Tables (LUTs).

Any suggestions?


Link to post

Here are some suggestions. Sorry I don't have time to understand your code and rewrite some of it to illustrate these ideas.

- Wherever possible, read from and write to IO and memory in a single location, to avoid arbitration, even if the code logically can't possibly execute multiple occurrences in parallel. It's fine to read memory in one location and write it somewhere else, but for each memory block I would try to have a single instance of the memory read, even if that means you read and discard the data most of the time. Likewise, move reading the digital inputs outside the case structure.

- In order to move the digital inputs outside the case structure, you'll need to restructure your state machine. I would create a lot more states, replacing the nested while loops with their own states where you don't proceed to the next state until the trigger occurs.

- Once you've done that, you can probably make the upper loop into a single-cycle timed loop (unless the analog outputs don't support it, which you could work around by putting them in their own loop and setting their value through a register). That should save you some FPGA space.


I would also check your logic. As far as I can tell, both TriggerPulses and the shift register value to which it's compared in the "Wait for Falling Trigger" case never change, so I don't see how you would ever move on from that case, unless the host updates the TriggerPulses value.

Link to post
  • Solution

Both of your FIFOs are massive, both to and from the FPGA.  They can be MUCH smaller.


What does your compile report look like, can you post a screenshot?

Yeah, problem seems to be distributed RAM LUT cells, of which you only have 11000 ont he device.


Your two FIFOs to and from the FPGA can be way way smaller, like 50 elements.


You have set them to use Block RAM but I don't think the compiler is doing that.

  • Like 2
Link to post

You're correct.

It looks like I'm running out of memory.

I have enough Block Memory, but it looks like it’s using LUTs instead, so yes by reducing the FIFO sizes it starts to compile.

The error message I get is: “The Design requires more LUT as Memory cells…This design requires 19337 of such cell types but only 17400 compatible sites are available in the target device.â€

I just reduce the FIFO to the FPGA and that solved it.

The problem was that I made the FIFO size to the FPGA too big, that design would make the SW easier just One Write on the RT, but now I need to do something like this in the RT:


Link to post
The problem was that I made the FIFO size to the FPGA too big, that design would make the SW easier just One Write on the RT

That's not necessary. The FIFO size on the host side is independent of the FIFO size on the FPGA. You can configure the host-side buffer to be much larger and then do a single write as you originally intended. The DMA automatically copies data from the host buffer into the FPGA buffer as space becomes available.

Link to post

Way to go and mark your own answer rather than the dude that actually solved it. :angry:

Not even a like for Shoneill? :shifty:

Sorry about that, both are marked as the solution now. He pointed me in the right direction and my solution just showed how I had to implement it to get it working.


That's not necessary. The FIFO size on the host side is independent of the FIFO size on the FPGA. You can configure the host-side buffer to be much larger and then do a single write as you originally intended. The DMA automatically copies data from the host buffer into the FPGA buffer as space becomes available.

Interesting idea.

So you can configure the FIFO in RT with the "Requestes Depth" to a much larger number that the FIFO on the FPGA supports, and the DMA will take care of the rest?!!?

If so that is a very nice solution.

Link to post

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Similar Content

    • By Ricardo de Abreu
      Hi guys. This semester I'm starting a course system development for control and automation engineering, witch will be based on LabView. Therefore, my University doesn't have a NI hardware, even a MyRIO for us to test our VI and the teacher said that we should test our projects with our own Arduino...
      So, I have a little experience in Arduino and I know the basics for LabView. Now I'm in a point that I know that with Arduino I'll not take the best from LabView. I cannot even deploy a code to it.
      So, there is where my question comes in...
      I'm looking for a new board better then Arduino to use in the classes. I would buy a MyRIO card if I had the money but in Brazil this board is too expensive for me
       Witch one should I get that is closest to myRIO and less expensive than that? I would like to try de deployment of a VI and FPGA..... Is this possible?
      Thanks a lot for the help!
    • By grjgrj
      Hello. I need change some code for SbRIO-9626 with LabVIEW 2018. I have code from LabVIEW 2015. Right now I have only LabVIEW 2018. And I worked with it for SbRIO-9627.
      LabVIEW FPGA, LabVIEW Real-Time, NICRIO1800 driver istalled.
      And I install Xilinx ISE 11.5 Compilation Tool too. 
      When I start compilation FPGA VI I got error about problem with compilation too (see attachment picture).
      Could you tell me how I can solve this problem? 
      It is very important. 

    • By prabhakaran
      I am trying to use image convolution inside FPGA. My Image size is around 6kx2k. The convolution is applied properly until 2600 pixels in x resolution. After that, the values seem to miss previous row data. 
      In Detail: As convolution is matrix operation, image data needs to be stored for the operation. But it seems there is an inadvertent error storing only 2600 pixels per row inside FPGA. And hence the filtered output is calculated assuming these pixels to be 0. 
      I have tried with different image sizes, different convolution kernels, and also in different targets (cRIO 9030 and IC 3173). All results are same.
      I have attached a screenshot of FPGA VI and an example image.
      The example image shows an input image of 4000x2500 of same pixel value 16.The kernel is 3x3 of values 1 with divider=1. The RT image is processed using IMAQ convolute inside RT controller and has value 144 [(9*16)/1] for all pixels. But the FPGA processed image (zoomed in) has 144 until 2597 pixels and then 112 (7*16- showing 1 column of 2 rows missing) at 2598, 80 (5*16- showing 2 columns of 2 rows missing) at 2599 and 48 after that (missing 3 columns of 2 rows- current row is always present). This shows the data is missing from the previous rows after 2600 index.
      Is there some mistake in the code or any workaround available?

    • By tdavid
      If I generate an FPGA IP core from my LabVIEW code, can I use it somehow in traditional FPGA development environments, such as Vivado?
    • By Nala
      Hello everybody,

      I'm about to write an application that can create a complete new FPGA-Project for the cRIO-system automatically without any user Input.

      Before I ask my question directly, I will give you a few Information about the system and how it works at the moment.
      I'm working with a cRIO-system that can have different modules in different slots (max 8). That system should be universally usable which means I can replace one module with another one at the start up and create a complete new project with a different name.

      Most of the project works (I can find out in which slots which module is placed and load the right VI's correctly) but there is one point which I really dislike: the user always has to give some input Information at the beginning of the creation and mostly that is the same like "Which type of project it should be" or "Which IP address should be used to find the system and the modules for each slot".

      The goal is that I can write down some specific arguments so the program is created automatically?
      Or - if there is no way to do this - a way that a second window is shown on screen to help the user through the creation process (for example that tells the user that the system need to be turned on that the project can find every single module)?

      English isn't my mother tongue, so please apologize if there are any mistakes in my spelling.
      Thank you very much for your help
  • Create New...

Important Information

By using this site, you agree to our Terms of Use.