Jump to content

7935R MGT Aurora Compilation Error -250514


Recommended Posts

I'm at a loss for what could be happening so I'm hoping somebody else has done something similar. I am using LabVIEW 2015 SP1 with the FlexRIO 15.5 drivers with the 7935R and receive an internal software error when trying to compile the example project "NI793xR - MGT Aurora CLIP.lvproj" when generating intermediate files. The Error I'm getting is copied below.

Code Gen Error.png

Error -250514 occurred at

Possible reason(s):

An AXI4-Lite address map element cannot fit in the specified address collection. Make sure that each address map elements' offset plus size does not exceed the address collection's total size.

My goal is to replace the DRAM FIFO that is currently being used to write to Port 0 with a Count Up, Count Down, or PRBS signal. I was receiving the same compilation error after trying to make these changes. I tried to be very careful with what I replaced and was pretty confident that I hadn't touched any of the AXI4 functions. I tried compiling the example project because I was going to start over and make sure I had a good starting point. The example does run but that's using the bitfile that's already compiled. I've tried compiling using the cloud as well as a company compile server. I'm also installing software so I can try this on another computer. I don't think I need the tools locally for this but I might try installing those to double check.

Pretty much out of ideas and wasn't able to find much online so any help would be appreciated.

 

Matt J

Edit: Same compilation error on second computer with local tools, both Windows 7.

Link to post

Got it working, just needed to ask someone who knew what they were looking at.

I needed to make a change to the "Create AXI4-Lite Resources.vi" which is next to the instruction framework interface on the FPGA.

arg.PNG

The Address Space Size is 0x800 by default so it just needs to be made larger. I compiled successfully at 0x1600 but I was told the correct size is 0x1200.

 

Matt J

  • Like 1
Link to post

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Similar Content

    • By Ricardo de Abreu
      Hi guys. This semester I'm starting a course system development for control and automation engineering, witch will be based on LabView. Therefore, my University doesn't have a NI hardware, even a MyRIO for us to test our VI and the teacher said that we should test our projects with our own Arduino...
      So, I have a little experience in Arduino and I know the basics for LabView. Now I'm in a point that I know that with Arduino I'll not take the best from LabView. I cannot even deploy a code to it.
      So, there is where my question comes in...
      I'm looking for a new board better then Arduino to use in the classes. I would buy a MyRIO card if I had the money but in Brazil this board is too expensive for me
       Witch one should I get that is closest to myRIO and less expensive than that? I would like to try de deployment of a VI and FPGA..... Is this possible?
      Thanks a lot for the help!
      Regards
    • By grjgrj
      Hello. I need change some code for SbRIO-9626 with LabVIEW 2018. I have code from LabVIEW 2015. Right now I have only LabVIEW 2018. And I worked with it for SbRIO-9627.
      LabVIEW FPGA, LabVIEW Real-Time, NICRIO1800 driver istalled.
      And I install Xilinx ISE 11.5 Compilation Tool too. 
      When I start compilation FPGA VI I got error about problem with compilation too (see attachment picture).
      Could you tell me how I can solve this problem? 
      It is very important. 

    • By prabhakaran
      Hi,
       
       
      I am trying to use image convolution inside FPGA. My Image size is around 6kx2k. The convolution is applied properly until 2600 pixels in x resolution. After that, the values seem to miss previous row data. 
       
      In Detail: As convolution is matrix operation, image data needs to be stored for the operation. But it seems there is an inadvertent error storing only 2600 pixels per row inside FPGA. And hence the filtered output is calculated assuming these pixels to be 0. 
       
      I have tried with different image sizes, different convolution kernels, and also in different targets (cRIO 9030 and IC 3173). All results are same.
       
      I have attached a screenshot of FPGA VI and an example image.
       
      The example image shows an input image of 4000x2500 of same pixel value 16.The kernel is 3x3 of values 1 with divider=1. The RT image is processed using IMAQ convolute inside RT controller and has value 144 [(9*16)/1] for all pixels. But the FPGA processed image (zoomed in) has 144 until 2597 pixels and then 112 (7*16- showing 1 column of 2 rows missing) at 2598, 80 (5*16- showing 2 columns of 2 rows missing) at 2599 and 48 after that (missing 3 columns of 2 rows- current row is always present). This shows the data is missing from the previous rows after 2600 index.
       
      Is there some mistake in the code or any workaround available?


    • By tdavid
      Hi,
      If I generate an FPGA IP core from my LabVIEW code, can I use it somehow in traditional FPGA development environments, such as Vivado?
      Thanks,
      David
    • By Nala
      Hello everybody,

      I'm about to write an application that can create a complete new FPGA-Project for the cRIO-system automatically without any user Input.

      Before I ask my question directly, I will give you a few Information about the system and how it works at the moment.
      I'm working with a cRIO-system that can have different modules in different slots (max 8). That system should be universally usable which means I can replace one module with another one at the start up and create a complete new project with a different name.

      Most of the project works (I can find out in which slots which module is placed and load the right VI's correctly) but there is one point which I really dislike: the user always has to give some input Information at the beginning of the creation and mostly that is the same like "Which type of project it should be" or "Which IP address should be used to find the system and the modules for each slot".

      The goal is that I can write down some specific arguments so the program is created automatically?
      Or - if there is no way to do this - a way that a second window is shown on screen to help the user through the creation process (for example that tells the user that the system need to be turned on that the project can find every single module)?

      English isn't my mother tongue, so please apologize if there are any mistakes in my spelling.
      Thank you very much for your help
×
×
  • Create New...

Important Information

By using this site, you agree to our Terms of Use.