Accessing FPGA Indicator Latency (cRIO)

[Yohann]

Hello,

I'm currently encountering a problem when accessing FPGA indicator with "Reading/ writing a control" node

The FPGA part acquires data every 10µs

The RT part Read the indicator every 2000µs

But when Running the VIs, I see that the elapsed time between 2 Readings of the indicator change from one iteration to another

Can someone help me?

[infinitenothing]

What sort of jitter are you seeing? What were you expecting? How much can you tolerate?

If you have to have better jitter try:

1. Move the indicators outside the loop. When you write to an indicator in development mode, it needs to use the network. You might also want to move the controls outside too and use something like a single process single element RT FIFO shared variable
2. Turn off debug
3. Replace the while loop with a timed loop

[ShaunR]

Sequence the wait and time functions using a sequence to ensure they are executed the in the same order, each time, on each iteration.

A better approach is to use the "Timed Loop" instead of the wait.